Inventor
YUNG-CHEN CHIEN
Inventor
TW
Overview
Patents· 30 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing24%
H03KPulse technique23%
H01LSemiconductor devices14%
H10DInorganic electric semiconductor devices14%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1014%
G01RMeasuring electric variables5%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use5%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h101%
PatentTitleYear
12,593,497Integrated circuit in hybrid row height structure202612,575,187Integrated circuit and method of forming the same202612,489,432Integrated circuit device, method and system202512,407,337Flip-flop circuit and method202512,369,389Integrated circuit in hybrid row height structure202512,355,446Data retention circuit and method202512,346,285Diagonal torus network202512,336,295Integrated circuit device and method202512,278,240IC logic device, layout, system, and method202512,243,741Semiconductor structure and method for forming the same202512,199,612Flip-flop with transistors having different threshold voltages, semiconductor device including same and methods of manufacturing same202512,107,581Clock gating circuit and method of operating the same202412,081,215Level shifter circuit and method of operating the same202412,074,069Semiconductor device and integrated circuit in hybrid row height structure202412,066,489Scan flip-flops with pre-setting combinational logic202412,047,079Flip-flop circuit and method202412,040,800Low hold multi-bit flip-flop202412,009,824Clock gating circuit and method of operating the same202411,979,158Integrated circuit device, method and system202411,907,007Clock signal distribution system, integrated circuit device and method202411,791,213Integrated circuit in hybrid row height structure202311,757,435Data retention circuit and method202311,715,733Integrated circuit device and method202311,677,400Level shifter circuit and method of operating the same202311,632,102Low-power flip-flop architecture with high-speed transmission gates202311,558,040Low hold multi-bit flip-flop202311,456,728Data retention circuit and method202211,362,660Level shifter circuit and method of operating the same202211,355,395Integrated circuit in hybrid row height structure202211,227,084Multi-bit standard cell2022Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2022–2026Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (30)· patent assignee history
2022–2026Based in TW· patent location history
2023Patents assigned to TAIWAN SEMICONDUCTOR MFG CAMPUS LTD (1)· patent assignee history
2025Patents assigned to ASSIER CONDUCTOR MFG COMPANY LTD (1)· patent assignee history
2025Patents assigned to TSMC NANJING COMPANY LTD (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 30 | 2022–2026 |
| ASSIER CONDUCTOR MFG COMPANY LTD | 1 | 2025 |
| TAIWAN SEMICONDUCTOR MFG CAMPUS LTD | 1 | 2023 |
| TSMC NANJING COMPANY LTD | 1 | 2025 |
Locations
| Location | Patents | Span |
|---|---|---|
| TW | 30 | 2022–2026 |