Inventor

John E. Sheets, II

Inventor

Zumbrota, MN, US

Overview

1999–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 149 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices22%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1019%

H01LSemiconductor devices12%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%

G06FElectric digital data processing10%

G11CStatic stores8%

G01RMeasuring electric variables3%

H03KPulse technique3%

H10BElectronic memory devices3%

H03MCoding2%

PatentTitleYear

11,061,645Optimizing data approximation analysis using low power circuitry2021 10,802,062Cognitive analysis using applied analog circuits2020 10,732,931Negative operand compatible charge-scaling subtractor circuit2020 10,670,642Real time cognitive monitoring of correlations between variables2020 10,671,348Charge-scaling multiplier circuit with dual scaled capacitor sets2020 10,663,502Real time cognitive monitoring of correlations between variables2020 10,658,993Charge-scaling multiplier circuit with digital-to-analog converter2020 10,598,710Cognitive analysis using applied analog circuits2020 10,592,209Charge-scaling multiplier circuit2020 10,587,282Charge-scaling adder circuit2020 10,566,987Charge-scaling subtractor circuit2020 10,418,094Predicting data correlation using multivalued logical outputs in static random access memory (SRAM) storage cells2019 10,367,520Charge-scaling subtractor circuit2019 10,348,320Charge-scaling adder circuit2019 10,304,522Method for low power operation and test using DRAM device2019 10,236,887Generating a unique die identifier for an electronic chip2019 10,236,050Optimizing data approximation analysis using low power circuitry2019 10,224,410Through-substrate via power gating and delivery bipolar transistor2019 10,224,089Optimizing data approximation analysis using low bower circuitry2019 10,170,578Through-substrate via power gating and delivery bipolar transistor2019 10,121,530Implementing eFuse visual security of stored data using EDRAM2018 10,090,063System for testing charge trap memory cells2018 10,061,368Enhancing performance of one or more slower partitions of an integrated circuit to improve performance of the integrated circuit2018 10,043,568Optimizing data approximation analysis using low power circuitry2018 10,037,792Optimizing data approximation analysis using low power circuitry2018 9,991,199Integrated shielding and decoupling capacitor structure2018 9,953,720Implementing hidden security key in eFuses2018 9,916,890'Predicting data correlation using multivalued logical outputs in static random access memory (SRAM) storage cells'2018 9,864,006'Generating a unique die identifier for an electronic chip'2018 9,721,856'Implementing resistance defect performance mitigation using test signature directed self heating and increased voltage'2017 9,712,112'Dynamic noise mitigation in integrated circuit devices using local clock buffers'2017 9,685,526'Side gate assist in metal gate first process'2017 9,666,305'System for testing charge trap memory cells'2017 9,646,712'Implementing eFuse visual security of stored data using EDRAM'2017 9,589,639'Multiple FET non-volatile memory with default logical state'2017 9,583,403'Implementing resistance defect performance mitigation using test signature directed self heating and increased voltage'2017 9,570,193'Implementing hidden security key in eFuses'2017 9,514,841'Implementing eFuse visual security of stored data using EDRAM'2016 9,496,326'High-density integrated circuit via capacitor'2016 9,496,045'Sensing of non-volatile memory cell having two complementary memory transistors'2016 9,455,313'High-density integrated circuit via capacitor'2016 9,443,767'Structure for metal oxide semiconductor capacitor'2016 9,424,948'Detection of initial state by eFuse array'2016 9,378,836'Sensing circuit for a non-volatile memory cell having two complementary memory transistors'2016 9,369,308'Signal transmission reducing coupling caused delay variation'2016 9,343,464'Implementing eDRAM stacked FET structure'2016 9,312,272'Implementing buried FET utilizing drain of finFET as gate of buried FET'2016 9,252,083'Semiconductor chip with power gating through silicon vias'2016 9,252,100'Multiple-patterned semiconductor device channels'2016 9,245,884'Structure for metal oxide semiconductor capacitor'2016 9,196,671'Integrated decoupling capacitor utilizing through-silicon via'2015 9,153,638'Integrated decoupling capacitor utilizing through-silicon via'2015 9,111,935'Multiple-patterned semiconductor device channels'2015 9,105,639'Semiconductor device channels'2015 9,099,533'Semiconductor device with distinct multiple-patterned conductive tracks on a same level'2015 9,099,462'Signal path and method of manufacturing a multiple-patterned semiconductor device'2015 9,099,164'Capacitor backup for SRAM'2015 9,099,471'Semiconductor device channels'2015 9,093,451'Signal path and method of manufacturing a multiple-patterned semiconductor device'2015 9,093,421'Implementing gate within a gate utilizing replacement metal gate process'2015 9,087,879'Method of making semiconductor device with distinct multiple-patterned conductive tracks on a same level'2015 9,082,624'Signal path of a multiple-patterned semiconductor device'2015 9,076,848'Semiconductor device channels'2015 9,070,751'Semiconductor device channels'2015 9,059,020'Implementing buried FET below and beside FinFET on bulk substrate'2015 9,059,307'Method of implementing buried FET below and beside FinFET on bulk substrate'2015 9,048,123'Interdigitated finFETs'2015 9,040,406'Semiconductor chip with power gating through silicon vias'2015 9,024,387'FinFET with body contact'2015 9,018,713'Plural differential pair employing FinFET structure'2015 9,021,407'Signal path of a multiple-patterned semiconductor device'2015 8,953,365'Capacitor backup for SRAM'2015 8,921,199'Precision IC resistor fabrication'2014 8,895,436'Implementing enhanced power supply distribution and decoupling utilizing TSV exclusion zone'2014 8,890,083'Soft error detection'2014 8,866,306'Signal path and method of manufacturing a multiple-patterned semiconductor device'2014 8,823,090'Field-effect transistor and method of creating same'2014 8,816,470'Independently voltage controlled volume of silicon on a silicon on insulator chip'2014 8,809,156'Method for implementing deep trench enabled high current capable bipolar transistor for current switching and output driver applications'2014 8,754,417'Vertical stacking of field effect transistor structures for logic gates'2014 8,754,499'Semiconductor chip with power gating through silicon vias'2014 8,735,975'Implementing semiconductor soc with metal via gate node high performance stacked transistors'2014 8,642,456'Implementing semiconductor signal-capable capacitors with deep trench and TSV technologies'2014 8,617,939'Enhanced thin film field effect transistor integration into back end of line'2013 8,592,921'Deep trench embedded gate transistor'2013 8,574,982'Implementing eDRAM stacked FET structure'2013 8,575,613'Implementing vertical signal repeater transistors utilizing wire vias as gate nodes'2013 8,571,847'Efficiency of static core turn-off in a system-on-a-chip with variation'2013 8,549,363'Reliability and performance of a system-on-a-chip by predictive wear-out based activation of functional components'2013 8,539,425'Utilizing gate phases for circuit tuning'2013 8,536,587'Method and apparatus for measurement and control of photomask to substrate alignment'2013 8,536,632'FinFET with reduced gate to fin overlay sensitivity'2013 8,535,393'Method and apparatus for measurement and control of photomask to substrate alignment'2013 8,525,245'eDRAM having dynamic retention and performance tradeoff'2013 8,518,767'FinFET with reduced gate to fin overlay sensitivity'2013 8,513,815'Implementing integrated circuit mixed double density and high performance wire structure'2013 8,492,220'Vertically stacked FETs with series bipolar junction transistor'2013 8,492,207'Implementing eFuse circuit with enhanced eFuse blow operation'2013 8,492,903'Through silicon via direct FET signal gating'2013 8,466,024'Power domain controller with gated through silicon via having FET with horizontal channel'2013 8,456,187'Implementing temporary disable function of protected circuitry by modulating threshold voltage of timing sensitive circuit'2013 8,435,851'Implementing semiconductor SoC with metal via gate node high performance stacked transistors'2013 8,395,186'Implementing vertical signal repeater transistors utilizing wire vias as gate nodes'2013 8,384,414'Implementing hacking detection and block function at indeterminate times with priorities and limits'2013 8,314,001'Vertical stacking of field effect transistor structures for logic gates'2012 8,214,657'Resistance sensing for defeating microchip exploitation'2012 8,172,140'Doped implant monitoring for microchip tamper detection'2012 8,138,054'Enhanced field effect transistor'2012 8,114,747'Method for creating 3-D single gate inverter'2012 8,105,940'Power distribution in a vertically integrated circuit'2012 8,107,309'Bias temperature instability-influenced storage cell'2012 8,079,134'Method of enhancing on-chip inductance structure utilizing silicon through via technology'2011 7,989,918'Implementing tamper evident and resistant detection through modulation of capacitance'2011 7,935,629'Semiconductor scheme for reduced circuit area in a simplified process'2011 7,935,546'Method and apparatus for measurement and control of photomask to substrate alignment'2011 7,915,949'Implementing eFuse resistance determination before initiating eFuse blow'2011 7,868,391'3-D single gate inverter'2011 7,865,859'Implementing APS voltage level activation with secondary chip in stacked-chip technology'2011 7,727,887'Method for improved power distribution in a three dimensional vertical integrated circuit'2010 7,723,816'Implementing decoupling capacitors with hot-spot thermal reduction on integrated circuit chips'2010 7,701,064'Apparatus for improved power distribution in a three dimensional vertical integrated circuit'2010 7,701,244'False connection for defeating microchip exploitation'2010 7,696,565'FinFET body contact structure'2010 7,626,220'Semiconductor scheme for reduced circuit area in a simplified process'2009 7,541,829'Method for correcting for asymmetry of threshold voltage shifts'2009 7,514,276'Aligning stacked chips using resistance assistance'2009 7,453,272'Electrical open/short contact alignment structure for active region vs. gate region'2008 7,336,086'Measurement of bias of a silicon area using bridging vertices on polysilicon shapes to create an electrical open/short contact structure'2008 7,317,605'Method and apparatus for improving performance margin in logic paths'2008 7,317,217'Semiconductor scheme for reduced circuit area in a simplified process'2008 7,241,649'FinFET body contact structure'2007 7,227,183'Polysilicon conductor width measurement for 3-dimensional FETs'2007 7,183,780'Electrical open/short contact alignment structure for active region vs. gate region'2007 7,050,871'Method and apparatus for implementing silicon wafer chip carrier passive devices'2006 7,009,905'Method and apparatus to reduce bias temperature instability (BTI) effects'2006 6,774,734'Ring oscillator circuit for EDRAM/DRAM performance monitoring'2004 6,670,716'Silicon-on-insulator (SOI) semiconductor structure for implementing transistor source connections using buried dual rail distribution'2003 6,667,518'Method and semiconductor structure for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices'2003 6,645,796'Method and semiconductor structure for implementing reach through buried interconnect for silicon-on-insulator (SOI) devices'2003 6,635,518'SOI FET and method for creating FET body connections with high-quality matching characteristics and no area penalty for partially depleted SOI technologies'2003 6,528,853'Method and semiconductor structure for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors'2003 6,498,057'Method for implementing SOI transistor source connections using buried dual rail distribution'2002 6,492,244'Method and semiconductor structure for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices'2002 6,429,099'Implementing contacts for bodies of semiconductor-on-insulator transistors'2002 6,287,901'Method and semiconductor structure for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors'2001 6,121,659'Buried patterned conductor planes for semiconductor-on-insulator integrated circuit'2000 6,043,689'Driver circuit for providing reduced AC defects'2000 5,889,306'Bulk silicon voltage plane for SOI applications'1999 5,872,697'Integrated circuit having integral decoupling capacitor'1999

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1999–2021Patents assigned to IBM (147)· patent assignee history

1999–2021Based in Zumbrota, MN, US· patent location history

2012–2015Patents assigned to SHEETS II JOHN E (24)· patent assignee history

2012–2015Patents assigned to PAULSEN DAVID P (20)· patent assignee history

2012–2015Patents assigned to WILLIAMS KELLY L (17)· patent assignee history

2013–2015Patents assigned to PAONE PHIL C (15)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	147	1999–2021
SHEETS II JOHN Eself	24	2012–2015
PAULSEN DAVID P	20	2012–2015
WILLIAMS KELLY L	17	2012–2015
PAONE PHIL C	15	2013–2015

Locations

Location	Patents	Span
Zumbrota, Minnesota, US	149	1999–2021