Inventor
Carl H. Carmichael
Inventor
San Jose, CA, US
Overview
Patents· 16 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing36%
G11CStatic stores21%
H03KPulse technique11%
G05BControl or regulating systems in general7%
H10BElectronic memory devices7%
H10DInorganic electric semiconductor devices7%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%
G01RMeasuring electric variables4%
PatentTitleYear
7,990,173'Single event upset mitigation'20117,650,585'Implementing a user design in a programmable logic device with single event upset mitigation'20107,626,415'Method and apparatus for configuring an integrated circuit'20097,620,883'Techniques for mitigating, detecting, and correcting single event upset effects'20097,589,558'Method and apparatus for configuring an integrated circuit'20097,576,557'Method and apparatus for mitigating one or more event upsets'20097,512,871'Techniques for mitigating, detecting, and correcting single event upset effects in systems using SRAM-based field programmable gate arrays'20097,452,765'Single event upset in SRAM cells in FPGAs with high resistivity gate structures'20087,383,479'Techniques for mitigating, detecting, and correcting single event upset effects in systems using SRAM-based field programmable gate arrays'20087,310,759'Techniques for mitigating, detecting, and correcting single event upset effects in systems using SRAM-based field programmable gate arrays'20077,249,010'Methods of estimating susceptibility to single event upsets for a design implemented in an FPGA'20077,036,059'Techniques for mitigating, detecting and correcting single event upset effects in systems using SRAM-based field programmable gate arrays'20066,982,451'Single event upset in SRAM cells in FPGAs with high resistivity gate structures'20066,560,665'Embedding firmware for a microprocessor with configuration data for a field programmable gate array'20036,425,077'System and method for reading data from a programmable logic device'20026,308,311'Method for reconfiguring a field programmable gate array from a host'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2011Patents assigned to XILINX INC (16)· patent assignee history
2001–2006Based in Campbell, CA, US· patent location history
2006–2011Based in San Jose, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| XILINX INC | 16 | 2001–2011 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 12 | 2006–2011 |
| Campbell, California, US | 4 | 2001–2006 |