Inventor
Robert Yung
Inventor
Fremont, CA, US
Overview
Patents· 25 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing73%
G06TImage data processing or generation, in general18%
G11CStatic stores6%
G09GArrangements or circuits for control of indicating devices using static means to present variable information3%
PatentTitleYear
6,396,504'Graphical image data reformatting method and apparatus'20026,385,713'Microprocessor with parallel inverse square root logic for performing graphics function on packed data elements'20026,304,961'Computer system and method for fetching a next instruction'20016,279,099'Central processing unit with integrated graphics functions'20016,205,538'Instruction result labeling in a counterflow pipeline processor'20016,128,721'Temporary pipeline register file for a superpipelined superscalar processor'20005,996,066'Partitioned multiply and add/subtract instruction for CPU with integrated graphics functions'19995,956,747'Processor having a plurality of pipelines and a mechanism for maintaining coherency among register values in the pipelines'19995,938,756'Central processing unit with integrated graphics functions'19995,933,157'Central processing unit with integrated graphics functions'19995,931,945'Graphic system for masking multiple non-contiguous bytes having decode logic to selectively activate each of the control lines based on the mask register bits'19995,918,245'Microprocessor having a cache memory system using multi-level cache set prediction'19995,809,324'Multiple instruction dispatch system for pipelined microprocessor without branch breaks'19985,761,472'Interleaving block operations employing an instruction set capable of delaying block-store instructions related to outstanding block-load instructions in a computer system'19985,761,475'Computer processor having a register file with reduced read and/or write port bandwidth'19985,752,271'Method and apparatus for using double precision addressable registers for single precision data'19985,734,874'Central processing unit with integrated graphics functions'19985,727,219'Virtual input/output processor utilizing an interrupt handler'19985,721,868'Rapid register file access by limiting access to a selectable register subset'19985,717,896'Method and apparatus for performing pipeline store instructions using a single cache access pipestage'19985,682,493'Scoreboard table for a counterflow pipeline processor with instruction packages and result packages'19975,592,679'Apparatus and method for distributed control in a processor architecture'19975,548,739'Method and apparatus for rapidly retrieving data from a physically addressed data storage structure using address page crossing predictive annotations'19965,546,554'Apparatus for dynamic register management in a floating point unit'19965,392,414'Rapid data retrieval from data storage structures using prior access predictive annotations'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995–2002Patents assigned to SUN MICROSYSTEMS INC (25)· patent assignee history
1995–2002Based in Fremont, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SUN MICROSYSTEMS INC | 25 | 1995–2002 |
Locations
| Location | Patents | Span |
|---|---|---|
| Fremont, California, US | 25 | 1995–2002 |