Inventor
Aman Bhatia
Inventor
San Jose, CA, US
Overview
Patents· 56 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Mprimary
H03MCoding36%
G06FElectric digital data processing30%
G11CStatic stores25%
H04LTransmission of digital information, e.g. telegraphic communication5%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%
G06NComputing arrangements based on specific computational models2%
G05BControl or regulating systems in general1%
PatentTitleYear
11,128,633Microservice deployment202111,057,282Microservice generation system202111,036,579Decoder for memory system and method thereof202111,025,283Decoding latency and throughput of a multi-decoder error correction system202110,877,840Dynamic neighbor and bitline assisted correction for NAND flash storage202010,846,172Encoding method and system for memory device including QLC cells202010,847,231Memory system with adaptive read-threshold scheme and method of operating such memory system202010,817,373Soft chip-kill recovery using concatenated codes202010,714,195Read disturb detection and recovery with adaptive thresholding for 3-D NAND storage202010,707,899Bit-flipping decoder for G-LDPC codes with syndrome-decoding for component codes202010,700,706Memory system with decoders and method of operating such memory system and decoders202010,693,496Memory system with LDPC decoder and method of operating such memory system and LDPC decoder202010,691,536Method to select flash memory blocks for refresh after read operations202010,691,540Soft chip-kill recovery for multiple wordlines failure202010,680,647Min-sum decoding for LDPC codes202010,672,497Memory system and method for bad block management202010,601,546Dynamic interleaver change for bit line failures in NAND flash storage202010,572,342Memory system with LDPC decoder and operating method thereof202010,523,245Soft decoder for generalized product codes201910,498,366Data dependency mitigation in parallel decoders for flash storage201910,491,243Deep learning for low-density parity-check (LDPC) decoding201910,484,008Memory system with on-the-fly error detection and termination and operating method thereof201910,484,020System and method for parallel decoding of codewords sharing common data201910,447,302Memory system decoding design and operating method thereof201910,439,649Data dependency mitigation in decoder architecture for generalized product codes for flash storage201910,432,363Page health prediction using product codes decoder in NAND flash storage201910,419,024Early termination of low-density parity-check (LDPC) decoding201910,403,372Memory system with adaptive read-threshold scheme and method of operating such memory system201910,389,383Low-complexity LDPC encoder201910,388,400Generalized product codes for flash storage201910,382,064Efficient LDPC encoder for irregular code201910,348,335Miscorrection avoidance for turbo product codes201910,326,477Techniques for miscorrection detection for constituent codewords in product codes201910,326,473Symbol-based coding for NAND flash devices201910,303,364Techniques for low-latency chase decoding of turbo product codes with soft information201910,262,744Layer-based memory controller optimizations for three dimensional memory constructs201910,218,388Techniques for low complexity soft decoder for turbo product codes201910,205,469Low latency soft decoder architecture for generalized product codes201910,200,066Code reconstruction scheme for multiple code rate TPC decoder201910,187,086State-based decoding of product codes201910,169,141Modifiable stripe length in flash memory devices201910,163,515Memory system having feature boosting and operating method thereof201810,157,097Redundant bytes utilization in error correction code201810,153,785Generalized low-density parity-check (GLDPC) code with variable length constituents201810,148,287Bit-flipping LDPC decoding algorithm with hard channel information201810,090,862Hybrid soft decoding algorithm for multiple-dimension TPC codes201810,090,865Performance optimization in soft decoding of error correcting codes201810,084,485Soft decoder parameter optimization for product codes201810,079,613Data mapping scheme for generalized product codes201810,049,757Techniques for dynamically determining performance of read reclaim operations201810,033,407Optimization of low density parity-check code encoder based on a search for an independent set of nodes20189,998,148Techniques for low complexity turbo product code decoding20189,954,556Scheme to avoid miscorrection for turbo product codes20189,935,659Performance optimization in soft decoding for turbo product codes20189,906,241'Apparatus and method for turbo product codes'20189,906,240'One-shot decoder for two-error-correcting BCH codes'2018Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2018–2021Patents assigned to SK HYNIX INC (54)· patent assignee history
2018Patents assigned to SK HYNIX MEMORY SOLUTIONS INC (2)· patent assignee history
2018–2021Based in San Jose, CA, US· patent location history
2018Based in Milpitas, CA, US· patent location history
2019Based in Fremont, CA, US· patent location history
2021Patents assigned to SAP SE (2)· patent assignee history
2021Based in Sunnyvale, CA, US· patent location history
2021Based in Los Gatos, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SK HYNIX INC | 54 | 2018–2021 |
| SAP SE | 2 | 2021 |
| SK HYNIX MEMORY SOLUTIONS INC | 2 | 2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 51 | 2018–2021 |
| Sunnyvale, California, US | 2 | 2021 |
| Los Gatos, California, US | 1 | 2021 |
| Fremont, California, US | 1 | 2019 |
| Milpitas, California, US | 1 | 2018 |