Inventor

Jonathan B. Ballagh

Inventor

Boulder, CO, US

Overview

2005–2020

Patent span

Physics

Primary field (CPC G)

Patents· 51 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing72%

G06TImage data processing or generation, in general10%

G09GArrangements or circuits for control of indicating devices using static means to present variable information7%

H03KPulse technique5%

G01RMeasuring electric variables2%

H04LTransmission of digital information, e.g. telegraphic communication2%

H04WWireless communication networks2%

PatentTitleYear

10,673,795Methods and arrangements for content filtering2020 9,620,084'Method and apparatus of graphical object selection in a web browser'2017 9,208,174'Non-language-based object search'2015 9,141,255'Mosaic generation from user-created content'2015 8,947,452'Mechanism for displaying visual clues to stacking order during a drag and drop operation'2015 8,812,289'Simulation that transfers port values of a design block via a configuration block of a programmable device'2014 8,773,468'System and method for intuitive manipulation of the layering order of graphics objects'2014 8,487,932'Drawing figures in computer-based drawing applications'2013 8,427,483'Drawing figures in computer-based drawing applications'2013 8,224,638'Managing programmable device configuration'2012 8,207,969'Method of abstracting a graphical object in a line art style suitable for printing and artwork-coloring'2012 8,091,030'Method and apparatus of graphical object selection in a web browser'2012 8,082,139'Displaying signals of a design block emulated in hardware co-simulation'2011 7,934,185'Method of simulating bidirectional signals in a modeling system'2011 7,911,481'Method and apparatus of graphical object selection'2011 7,895,564'Using XTables to communicate in a high level modeling system'2011 7,870,522'Efficient communication of data between blocks in a high level modeling system'2011 7,797,677'Using scripts for netlisting in a high-level modeling system'2010 7,747,423'Systems and methods of co-simulation utilizing multiple PLDs in a boundary scan chain'2010 7,739,092'Fast hardware co-simulation reset using partial bitstreams'2010 7,707,019'Command buffering for hardware co-simulation'2010 7,636,653'Point-to-point ethernet hardware co-simulation interface'2009 7,590,137'Parameterizable compact network processor for low-level communication with an integrated circuit'2009 7,546,572'Shared memory interface in a programmable logic device using partial reconfiguration'2009 7,539,953'Method and apparatus for interfacing instruction processors and logic in an electronic circuit modeling system'2009 7,478,030'Clock stabilization detection for hardware simulation'2009 7,444,603'Transformation of graphs representing an electronic design in a high modeling system'2008 7,437,280'Hardware-based co-simulation on a PLD having an embedded processor'2008 7,433,813'Embedding a co-simulated hardware object in an event-driven simulator'2008 7,383,478'Wireless dynamic boundary-scan topologies for field'2008 7,376,544'Vector transfer during co-simulation'2008 7,366,998'Efficient communication of data between blocks in a high level modeling system'2008 7,366,651'Co-simulation interface'2008 7,363,600'Method of simulating bidirectional signals in a modeling system'2008 7,346,482'Shared memory for co-simulation'2008 7,346,481'Hardware co-simulation breakpoints in a high-level modeling system'2008 7,343,572'Vector interface to shared memory in simulating a circuit design'2008 7,328,421'Relocating blocks for netlist generation of an electronic system'2008 7,287,178'Communication between clock domains of an electronic circuit'2007 7,284,225'Embedding a hardware object in an application system'2007 7,269,811'Method of and apparatus for specifying clock domains in electronic circuit designs'2007 7,207,015'Translation of an electronic integrated circuit design into hardware'2007 7,203,632'HDL co-simulation in a high-level modeling system'2007 7,184,946'Co-simulation via boundary scan interface'2007 7,086,030'Incremental netlisting'2006 7,068,071'Integrated circuit with overclocked dedicated logic circuitry'2006 7,010,664'Configurable address generator and circuit using same'2006 7,007,261'Translation of an electronic integrated circuit design into hardware description language using circuit description template'2006 7,003,751'Specification of the hierarchy, connectivity, and graphical representation of a circuit design'2006 6,911,840'Integrated circuit with overclocked dedicated logic circuitry'2005 6,883,147'Method and system for generating a circuit design including a peripheral component connected to a bus'2005

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2005–2014Patents assigned to XILINX INC (40)· patent assignee history

2005–2011Based in Longmont, CO, US· patent location history

2008–2020Based in Boulder, CO, US· patent location history

2011–2020Patents assigned to DISNEY ENTPR INC (11)· patent assignee history

2011–2020Patents assigned to BALLAGH JONATHAN B (10)· patent assignee history

2012–2017Patents assigned to MILNE ROGER B (9)· patent assignee history

2012–2020Patents assigned to FISCHABER THOMAS E (7)· patent assignee history

2015Based in Leesburg, VA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
XILINX INC	40	2005–2014
DISNEY ENTPR INC	11	2011–2020
BALLAGH JONATHAN Bself	10	2011–2020
MILNE ROGER B	9	2012–2017
FISCHABER THOMAS E	7	2012–2020

Locations

Location	Patents	Span
Boulder, CO, US	26	2008–2020
Longmont, CO, US	24	2005–2011
Leesburg, Virginia, US	1	2015