Inventor
Senaka Kanakamedala
Inventor
San Jose, CA, US
Overview
Patents· 38 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices26%
H10BElectronic memory devices26%
H10DInorganic electric semiconductor devices21%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1013%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
G11CStatic stores2%
H10NElectric solid-state devices not otherwise provided for1%
H10KOrganic electric solid-state devices1%
PatentTitleYear
11,114,406Warpage-compensated bonded structure including a support chip and a three-dimensional memory chip202110,950,629Three-dimensional flat NAND memory device having high mobility channels and methods of making the same202110,910,272Reusable support substrate for formation and transfer of semiconductor devices and methods of using the same202110,847,408Warpage-compensated bonded structure including a support chip and a three-dimensional memory chip202010,748,925Three-dimensional memory device containing channels with laterally pegged dielectric cores202010,700,086Three-dimensional flat NAND memory device having high mobility channels and methods of making the same202010,622,369Three-dimensional memory device including contact via structures that extend through word lines and method of making the same202010,622,368Three-dimensional memory device with semicircular metal-semiconductor alloy floating gate electrodes and methods of making thereof202010,529,620Three-dimensional memory device containing word lines formed by selective tungsten growth on nucleation controlling surfaces and methods of manufacturing the same202010,468,596Damascene process for forming three-dimensional cross rail phase change memory devices201910,461,163Three-dimensional memory device with thickened word lines in terrace region and method of making thereof201910,453,854Three-dimensional memory device with thickened word lines in terrace region201910,438,964Three-dimensional memory device having direct source contact and metal oxide blocking dielectric and method of making thereof201910,381,364Three-dimensional memory device including vertically offset drain select level layers and method of making thereof201910,256,247Three-dimensional memory device with silicided word lines, air gap layers and discrete charge storage elements, and method of making thereof201910,199,434Three-dimensional cross rail phase change memory device and method of manufacturing the same201910,128,261Cobalt-containing conductive layers for control gate electrodes in a memory structure201810,050,054Three-dimensional memory device having drain select level isolation structure and method of making thereof20189,984,963Cobalt-containing conductive layers for control gate electrodes in a memory structure20189,893,081'Ridged word lines for increasing control gate lengths in a three-dimensional memory device'20189,824,966'Three-dimensional memory device containing a lateral source contact and method of making the same'20179,812,463'Three-dimensional memory device containing vertically isolated charge storage regions and method of making thereof'20179,806,090'Vertical floating gate NAND with selectively deposited ALD metal films'20179,691,884'Monolithic three dimensional NAND strings and methods of fabrication thereof'20179,659,955'Crystalinity-dependent aluminum oxide etching for self-aligned blocking dielectric in a memory structure'20179,646,990'NAND memory strings and methods of fabrication thereof'20179,627,399'Three-dimensional memory device with metal and silicide control gates'20179,570,460'Spacer passivation for high-aspect ratio opening film removal and cleaning'20179,570,455'Metal word lines for three dimensional memory devices'20179,484,357'Selective blocking dielectric formation in a three-dimensional memory structure'20169,478,558'Semiconductor structure with concave blocking dielectric sidewall and method of making thereof by isotropically etching the blocking dielectric layer'20169,397,107'Methods of making three dimensional NAND devices'20169,379,124'Vertical floating gate NAND with selectively deposited ALD metal films'20169,379,132'NAND memory strings and methods of fabrication thereof'20169,305,849'Method of making a three dimensional NAND device'20169,305,932'Methods of making three dimensional NAND devices'20169,236,396'Three dimensional NAND device and method of making thereof'20169,159,739'Floating gate ultrahigh density vertical NAND flash memory'2015Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2015–2018Patents assigned to SANDISK TECHNOLOGIES INC (15)· patent assignee history
2015–2021Based in San Jose, CA, US· patent location history
2016–2021Patents assigned to SANDISK TECHNOLOGIES LLC (32)· patent assignee history
2016–2020Based in Milpitas, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SANDISK TECHNOLOGIES LLC | 32 | 2016–2021 |
| SANDISK TECHNOLOGIES INC | 15 | 2015–2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 21 | 2015–2021 |
| Milpitas, California, US | 17 | 2016–2020 |