Inventor
Elias L. Fallon
Inventor
Allison Park, PA, US
Overview
Patents· 14 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing78%
G06NComputing arrangements based on specific computational models22%
PatentTitleYear
11,087,060System, method, and computer program product for the integration of machine learning predictors in an automatic placement associated with an electronic design202111,048,852System, method and computer program product for automatic generation of sizing constraints by reusing existing electronic designs202111,003,825System, method, and computer program product for optimization in an electronic design202110,699,051Method and system for performing cross-validation for model-based layout recommendations202010,628,546Method and system for automatically extracting layout design patterns for custom layout design reuse through interactive recommendations20209,298,871'Method and system for implementing translations of parameterized cells'20169,064,063'Methods, systems, and articles of manufacture for implementing interactive, real-time checking or verification of complex constraints'20158,732,640'Methods, systems, and articles for multi-scenario physically-aware design methodology for layout-dependent effects'20148,694,943'Methods, systems, and computer program product for implementing electronic designs with connectivity and constraint awareness'20147,543,262'Analog layout module generator and method'20097,093,220'Method for generating constrained component placement for integrated circuits and packages'20066,918,102'Method and apparatus for exact relative positioning of devices in a semiconductor circuit layout'20056,874,133'Integrated circuit design layout compaction method'20056,711,725'Method of creating conformal outlines for use in transistor level semiconductor layouts'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2005Based in Tempe, AZ, US· patent location history
2005–2021Patents assigned to CADENCE DESIGN SYSTEMS INC (13)· patent assignee history
2006–2009Based in Pittsburgh, PA, US· patent location history
2014–2016Patents assigned to FALLON ELIAS L (3)· patent assignee history
2014–2015Patents assigned to BAUDHUIN JOSHUA (2)· patent assignee history
2014–2015Patents assigned to COLWELL REGIS (2)· patent assignee history
2014–2015Patents assigned to DESHMANE HARSH (2)· patent assignee history
2014–2021Based in Allison Park, PA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| CADENCE DESIGN SYSTEMS INC | 13 | 2005–2021 |
| FALLON ELIAS Lself | 3 | 2014–2016 |
| BAUDHUIN JOSHUA | 2 | 2014–2015 |
| COLWELL REGIS | 2 | 2014–2015 |
| DESHMANE HARSH | 2 | 2014–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Allison Park, Pennsylvania, US | 9 | 2014–2021 |
| Tempe, AZ, US | 3 | 2004–2005 |
| Pittsburgh, Pennsylvania, US | 2 | 2006–2009 |