Inventor
Jaspreet S. Gandhi
Inventor
Boise, ID, US
Overview
Patents· 78 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1039%
H01LSemiconductor devices37%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
C23CCoating metallic material2%
G01RMeasuring electric variables2%
H05KPrinted circuits2%
H10HInorganic light-emitting semiconductor devices having potential barriers2%
B23KSoldering or unsoldering1%
C09DCoating compositions, e.g. paints, varnishes or lacquers1%
H10DInorganic electric semiconductor devices1%
PatentTitleYear
11,127,643Test structures for validating package fabrication process202111,114,360Multi-die device structures and methods202110,971,474Package integration for high bandwidth memory202110,930,611Solder joints for board level reliability202110,916,487Method for manufacturing a semiconductor device assembly with through-mold cooling channel formed in encapsulant202110,886,196Semiconductor devices having conductive vias and methods of forming the same202110,879,157High density substrate and stacked silicon package assembly having the same202010,861,825Interconnect structures with intermetallic palladium joints and associated systems and methods202010,847,382Solder bond site including an opening with discontinuous profile202010,770,430Package integration for memory devices202010,748,878Semiconductor device assembly with heat transfer structure formed from semiconductor material202010,741,468Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods202010,741,460Methods for forming interconnect assemblies with probed bond pads202010,692,733Uniform back side exposure of through-silicon vias202010,651,155Thermal pads between stacked semiconductor dies and associated systems and methods202010,593,638Methods of interconnect for high density 2.5D and 3D integration202010,580,746Bonding pads with thermal pathways202010,573,612Bonding pads with thermal pathways202010,559,551Semiconductor device assembly with heat transfer structure formed from semiconductor material202010,529,645Methods and apparatus for thermal interface material (TIM) bond line thickness (BLT) reduction and TIM adhesion enhancement for efficient thermal management202010,527,670Testing system for lid-less integrated circuit packages202010,481,200Semiconductor device test apparatuses comprising at least one test site having an array of pockets201910,424,531Method for manufacturing a semiconductor device assembly with through-mold cooling channel formed in encapsulant201910,410,882Solder bond site including an opening with discontinuous profile201910,410,879Uniform back side exposure of through-silicon vias201910,403,591Chip package assembly with enhanced interconnects and method for fabricating the same201910,319,606Chip package assembly with enhanced interconnects and method for fabricating the same201910,297,577Semiconductor device assembly with heat transfer structure formed from semiconductor material201910,262,922Semiconductor device having through-silicon-via and methods of forming the same201910,256,216Interconnect structures with intermetallic palladium joints and associated systems and methods201910,236,229Stacked silicon package assembly having conformal lid201910,224,313Interconnect structures with intermetallic palladium joints and associated systems and methods201910,170,389Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods201910,163,755Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths201810,163,830Bonding pads with thermal pathways201810,134,647Methods for forming interconnect assemblies with probed bond pads201810,126,357Methods of testing semiconductor devices comprising a die stack having protruding conductive elements201810,096,579Thermal pads between stacked semiconductor dies and associated systems and methods201810,096,502Method and apparatus for assembling and testing a multi-integrated circuit package20189,966,347Under-bump metal structures for interconnecting semiconductor dies or packages and associated systems and methods20189,960,150Semiconductor device assembly with through-mold cooling channel formed in encapsulant20189,941,190Semiconductor device having through-silicon-via and methods of forming the same20189,905,539'Interconnect structures with intermetallic palladium joints and associated systems and methods'20189,881,858'Solder bond site including an opening with discontinuous profile'20189,881,886'Semiconductor device assemblies including intermetallic compound interconnect structures'20189,837,383Interconnect structure with improved conductive properties and associated systems and methods20179,837,396Stacked semiconductor die assemblies with high efficiency thermal paths and associated methods20179,818,622'Uniform back side exposure of through-silicon vias'20179,768,149'Semiconductor device assembly with heat transfer structure formed from semiconductor material'20179,768,147'Thermal pads between stacked semiconductor dies and associated systems and methods'20179,741,612'Semiconductor devices and methods for backside photo alignment'20179,733,304'Semiconductor device test apparatuses'20179,704,781'Under-bump metal structures for interconnecting semiconductor dies or packages and associated systems and methods'20179,691,746'Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths'20179,646,899'Interconnect assemblies with probed bond pads'20179,564,418'Interconnect structures with intermetallic palladium joints and associated systems and methods'20179,520,370'Methods of forming semiconductor device assemblies and interconnect structures, and related semiconductor device assemblies and interconnect structures'20169,515,002'Bonding pads with thermal pathways'20169,449,940'Methods and structures for processing semiconductor devices using polymeric materials and adhesives'20169,443,744'Stacked semiconductor die assemblies with high efficiency thermal paths and associated methods'20169,412,675'Interconnect structure with improved conductive properties and associated systems and methods'20169,362,143'Methods for forming semiconductor device packages with photoimageable dielectric adhesive material, and related semiconductor device packages'20169,337,119'Stacked semiconductor die assemblies with high efficiency thermal paths and associated systems'20169,318,438'Semiconductor structures comprising at least one through-substrate via filled with conductive materials'20169,299,663'Semiconductor devices and methods for backside photo alignment'20169,224,715'Methods of forming semiconductor die assemblies'20159,153,520'Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods'20159,123,700'Integrated circuit constructions having through substrate vias and methods of forming integrated circuit constructions having through substrate vias'20159,034,769'Methods of selectively removing a substrate material'20159,029,257'Semiconductor constructions and methods of planarizing across a plurality of electrically conductive posts'20158,970,034'Semiconductor assemblies and structures'20158,962,449'Methods for processing semiconductor devices'20158,872,356'Semiconductor structures comprising a dielectric material having a curvilinear profile'20148,729,590'Solid state lighting devices having side reflectivity and associated methods of manufacture'20148,519,516'Semiconductor constructions'20138,492,242'Dry flux bonding device and method'20138,436,386'Solid state lighting devices having side reflectivity and associated methods of manufacture'20137,994,249'Silane coating compositions and methods of use thereof'2011Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2011Based in North Olmsted, OH, US· patent location history
2013–2021Patents assigned to MICRON TECHNOLOGY INC (64)· patent assignee history
2013–2017Patents assigned to GANDHI JASPREET S (5)· patent assignee history
2013–2015Patents assigned to GANDHI JASPREET (3)· patent assignee history
2013–2020Based in Boise, ID, US· patent location history
2015–2017Patents assigned to ENGLAND LUKE G (2)· patent assignee history
2018–2021Patents assigned to XILINX INC (13)· patent assignee history
2018–2020Based in Milpitas, CA, US· patent location history
2019–2021Based in San Jose, CA, US· patent location history
2021Based in Union City, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 64 | 2013–2021 |
| XILINX INC | 13 | 2018–2021 |
| GANDHI JASPREET Sself | 5 | 2013–2017 |
| GANDHI JASPREETself | 3 | 2013–2015 |
| ENGLAND LUKE G | 2 | 2015–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Boise, ID, US | 51 | 2013–2020 |
| San Jose, California, US | 16 | 2019–2021 |
| Milpitas, California, US | 9 | 2018–2020 |
| Union City, California, US | 1 | 2021 |
| North Olmsted, OH, US | 1 | 2011 |