Inventor
Zhibin Ren
Inventor
Hopewell Junction, NY, US
Overview
Patents· 44 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices49%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1020%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1014%
H01LSemiconductor devices4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
H04MTelephonic communication3%
H10BElectronic memory devices3%
G01JMeasurement of intensity, velocity, spectral content, polarisation, phase or pulse characteristics of infrared, visible or ultraviolet light1%
H02SGeneration of electric power by conversion of infrared radiation, visible light or ultraviolet light, e.g. using photovoltaic [pv] modules1%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution1%
PatentTitleYear
11,002,597Solar spectrum sensor for determining value of solar spectrum based on determined average photon energy20219,634,084'Conformal buffer layer in source and drain regions of fin-type transistors'20178,946,028'Merged FinFETs and method of manufacturing the same'20158,809,187'Body contacts for FET in SOI SRAM array'20148,765,532'Fabrication of field effect devices using spacers'20148,637,381'High-k dielectric and silicon nitride box region'20148,575,699'Thin box metal backgate extremely thin SOI device'20138,546,920'Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX)'20138,462,916'Method, system and device for playing enterprise color ringback tone'20138,431,994'Thin-BOX metal backgate extremely thin SOI device'20138,410,544'finFETs and methods of making same'20138,338,292'Body contacts for FET in SOI SRAM array'20128,329,564'Method for fabricating super-steep retrograde well MOSFET on SOI or bulk silicon substrate, and device fabricated in accordance with the method'20128,314,463'Method for fabricating super-steep retrograde well MOSFET on SOI or bulk silicon substrate, and device fabricated in accordance with the method'20128,299,546'Semiconductor devices with vertical extensions for lateral scaling'20128,288,826'Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX)'20128,236,661'Self-aligned well implant for improving short channel effects control, parasitic capacitance, and junction leakage'20128,202,780'Method for manufacturing a FinFET device comprising a mask to define a gate perimeter and another mask to define fin regions'20128,198,673'Asymmetric epitaxy and application thereof'20128,149,998'Method, system and device for playing enterprise color ringback tone'20128,053,373'Semiconductor-on-insulator(SOI) structures including gradient nitrided buried oxide (BOX)'20118,043,920'finFETS and methods of making same'20118,021,956'Ultrathin SOI CMOS devices employing differential STI liners'20118,012,820'Ultra-thin SOI CMOS with raised epitaxial source and drain and embedded SiGe PFET extension'20117,993,995'Metal-gated MOSFET devices having scaled gate stack thickness including gettering species in a buried oxide'20117,989,297'Asymmetric epitaxy and application thereof'20117,968,459'Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors'20117,955,950'Semiconductor-on-insulator substrate with a diffusion barrier'20117,955,928'Structure and method of fabricating FinFET'20117,776,624'Method for improving semiconductor surfaces'20107,704,839'Buried stress isolation for high-performance CMOS technology'20107,687,863'Selective incorporation of charge for transistor channels'20107,659,583'Ultrathin SOI CMOS devices employing differential STI liners'20107,648,868'Metal-gated MOSFET devices having scaled gate stack thickness'20107,494,886'Uniaxial strain relaxation of biaxial-strained thin films using ion implantation'20097,476,579'Method and structure for enhancing both nMOSFET and pMOSFET performance with a stressed film'20097,459,752'Ultra thin body fully-depleted SOI MOSFETs'20087,396,776'Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX)'20087,384,851'Buried stress isolation for high-performance CMOS technology'20087,374,998'Selective incorporation of charge for transistor channels'20087,326,997'Method and structure for enhancing both nMOSFET and pMOSFET performance with a stressed film'20087,183,613'Method and structure for enhancing both NMOSFET and PMOSFET performance with a stressed film'20077,091,069'Ultra thin body fully-depleted SOI MOSFETs'20067,002,214'Ultra-thin body super-steep retrograde well (SSRW) FET devices'2006Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2006–2015Patents assigned to IBM (40)· patent assignee history
2006–2017Based in Hopewell Junction, NY, US· patent location history
2011–2013Based in Hopewell Jct., NY, US· patent location history
2012–2015Patents assigned to REN ZHIBIN (16)· patent assignee history
2012–2015Patents assigned to CHAN KEVIN K (7)· patent assignee history
2012–2015Patents assigned to WANG XINHUI (7)· patent assignee history
2012–2014Patents assigned to YIN HAIZHOU (3)· patent assignee history
2012–2013Based in Shenzhen, CN· patent location history
2021Based in Singapore, SG· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 40 | 2006–2015 |
| REN ZHIBINself | 16 | 2012–2015 |
| CHAN KEVIN K | 7 | 2012–2015 |
| WANG XINHUI | 7 | 2012–2015 |
| YIN HAIZHOU | 3 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hopewell Junction, New York, US | 38 | 2006–2017 |
| Hopewell Jct., New York, US | 3 | 2011–2013 |
| Shenzhen, CN | 2 | 2012–2013 |
| Singapore, SG | 1 | 2021 |