Inventor
Alexander Lidow
Inventor
Manhattan Beach, CA, US
Overview
Patents· 42 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices44%
H01LSemiconductor devices20%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1015%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems2%
H03KPulse technique2%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications2%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
H10HInorganic light-emitting semiconductor devices having potential barriers1%
PatentTitleYear
11,050,339Integrated circuit with multiple gallium nitride transistor sets202110,601,300Integrated gallium nitride based DC-DC converter202010,600,674Semiconductor devices with back surface isolation202010,312,260GaN transistors with polysilicon layers used for creating additional components201910,312,131Semiconductor devices with back surface isolation201910,312,335Gate with self-aligned ledge for enhancement mode GaN transistors20199,837,438GaN transistors with polysilicon layers used for creating additional components20179,748,347'Gate with self-aligned ledged for enhancement mode GaN transistors'20179,607,876'Semiconductor devices with back surface isolation'20179,583,480'Integrated circuit with matching threshold voltages and method for making same'20179,331,191'GaN device with reduced output capacitance and process for making same'20169,214,399'Integrated circuit with matching threshold voltages and method for making same'20159,214,461'GaN transistors with polysilicon layers for creating additional components'20159,214,528'Method to fabricate self-aligned isolation in gallium nitride devices and integrated circuits'20159,171,911'Isolation structure in gallium nitride devices and integrated circuits'20158,969,918'Enhancement mode gallium nitride transistor with improved gate characteristics'20158,890,168'Enhancement mode GaN HEMT device'20148,853,749'Ion implanted and self aligned gate structure for GaN transistors'20148,823,012'Enhancement mode GaN HEMT device with gate spacer and method for fabricating the same'20148,785,974'Bumped, self-isolated GaN transistor chip with electrically isolated back surface'20148,436,398'Back diffusion suppression structures'20138,404,508'Enhancement mode GaN HEMT device and method for fabricating the same'20138,368,120'Hybrid semiconductor device having a GaN transistor and a silicon MOSFET'20138,350,294'Compensated gate MISFET and method for fabricating the same'20138,017,978'Hybrid semiconductor device'20117,955,969'Ultra thin FET'20115,742,087'High power MOSFET with low on-resistance and high breakdown voltage'19985,598,018'High power MOSFET with low on-resistance and high breakdown voltage'19975,338,961'High power MOSFET with low on-resistance and high breakdown voltage'19945,191,396'High power MOSFET with low on-resistance and high breakdown voltage'19935,130,767'Plural polygon source pattern for mosfet'19925,008,725'Plural polygon source pattern for MOSFET'19914,959,699'High power MOSFET with low on-resistance and high breakdown voltage'19904,789,882'High power MOSFET with direct connection from connection pads to underlying silicon'19884,705,759'High power MOSFET with low on-resistance and high breakdown voltage'19874,680,853'Process for manufacture of high power MOSFET with laterally distributed high carrier density beneath the gate oxide'19874,642,666'High power MOSFET with low on-resistance and high breakdown voltage'19874,593,302'Process for manufacture of high power MOSFET with laterally distributed high carrier density beneath the gate oxide'19864,416,708'Method of manufacture of high speed, high power bipolar transistor'19834,412,242'Planar structure for high voltage semiconductor devices with gaps in glassy layer over high field regions'19834,399,449'Composite metal and polysilicon field plate structure for high voltage semiconductor devices'19834,376,286'High power MOSFET with low on-resistance and high breakdown voltage'1983Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1983–2013Patents assigned to INT RECTIFIER CORP (19)· patent assignee history
1983–1994Based in Manhattan Beach, CA, US· patent location history
1988–2013Based in Hermosa Beach, CA, US· patent location history
2013–2021Patents assigned to EFFICIENT POWER CONVERSION CORP (20)· patent assignee history
2013–2017Patents assigned to LIDOW ALEXANDER (9)· patent assignee history
2013–2017Patents assigned to BEACH ROBERT (8)· patent assignee history
2013–2017Patents assigned to CAO JIANJUN (8)· patent assignee history
2013–2017Based in Marina Del Ray, CA, US· patent location history
2015–2021Based in Marina Del Rey, CA, US· patent location history
2017–2020Based in Santa Monica, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| EFFICIENT POWER CONVERSION CORP | 20 | 2013–2021 |
| INT RECTIFIER CORP | 19 | 1983–2013 |
| LIDOW ALEXANDERself | 9 | 2013–2017 |
| BEACH ROBERT | 8 | 2013–2017 |
| CAO JIANJUN | 8 | 2013–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Manhattan Beach, California, US | 12 | 1983–1994 |
| Marina Del Ray, California, US | 10 | 2013–2017 |
| Marina Del Rey, California, US | 8 | 2015–2021 |
| Hermosa Beach, California, US | 6 | 1988–2013 |
| Santa Monica, California, US | 5 | 2017–2020 |