LexDanaLexDanabeta
Inventor

Stephen S. Pawlowski

Inventor
Beaverton, OR, US

Overview

60→
Patents
1993–2020
Patent span
Physics
Primary field (CPC G)

Patents· 60 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing89%
G11CStatic stores3%
G01SRadio direction-finding2%
H03GControl of amplification2%
H04LTransmission of digital information, e.g. telegraphic communication2%
H04WWireless communication networks2%
H05KPrinted circuits2%
PatentTitleYear
10,831,377Extended line width memory-side cache systems and methods202010,691,347Extended line width memory-side cache systems and methods202010,146,657Initialization trace of a computing device20189,547,615'Peripheral protocol negotiation'20177,831,819'Filter micro-coded accelerator'2010RE040921'Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system'20097,519,344'Bandpass amplifier, method, and system'20096,907,487'Enhanced highly pipelined bus architecture'20056,880,031'Snoop phase in a highly pipelined bus architecture'20056,807,592'Quad pumped bus architecture and protocol'20046,804,735'Response and data phases in a highly pipelined bus architecture'2004RE038388'Method and apparatus for performing deferred transactions'20046,609,171'Quad pumped bus architecture and protocol'20036,601,121'Quad pumped bus architecture and protocol'20036,594,756'Multi-processor system for selecting a processor which has successfully written it\'s ID into write-once register after system reset as the boot-strap processor'20036,557,071'Memory system including a memory controller having a data strobe generator and method for accesing a memory using a data storage'20036,487,655'Computer system formed with a processor and a system board provided with complementary initialization support'20026,446,154'Method and mechanism for virtualizing legacy sideband signals in a hub interface architecture'20026,418,496'System and apparatus including lowest priority logic to select a processor to receive an interrupt message'20026,415,367'Apparatus for reducing asynchronous service latency in a time slot-based memory arbitration scheme'20026,412,060'Method and apparatus for supporting multiple overlapping address spaces on a shared bus'20026,412,049'Method for minimizing CPU memory latency while transferring streaming data'20026,405,271'Data flow control mechanism for a bus supporting two-and three-agent transactions'20026,401,153'Mechanisms for converting interrupt request signals on address and data lines to interrupt message signals'20026,381,665'Mechanisms for converting interrupt request signals on address and data lines to interrupt message signals'20026,374,321'Mechanisms for converting address and data signals to interrupt message signals'20026,363,461'Apparatus for memory resource arbitration based on dedicated time slot allocation'20026,263,397'Mechanism for delivering interrupt messages'20016,253,302'Method and apparatus for supporting multiple overlapping address spaces on a shared bus'20016,219,741'Transactions supporting interrupt destination redirection and level triggered interrupt semantics'20016,195,712'Dynamic discovery of wireless peripherals'20016,178,206'Method and apparatus for source synchronous data transfer'20016,151,663'Cluster controller for memory and data cache in a multiple cluster processing system'20006,108,735'Method and apparatus for responding to unclaimed bus transactions'20006,012,118'Method and apparatus for performing bus operations in a computer system using deferred replies returned without using the address bus'20005,996,042'Scalable, high bandwidth multicard memory system utilizing a single memory controller'19995,978,737'Method and apparatus for hazard detection and distraction avoidance for a vehicle'19995,961,621'Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system'19995,956,516'Mechanisms for converting interrupt request signals on address and data lines to interrupt message signals'19995,923,857'Method and apparatus for ordering writeback data transfers on a bus'19995,919,254'Method and apparatus for switching between source-synchronous and common clock data transfer modes in a multiple processing system'19995,911,053'Method and apparatus for changing data transfer widths in a computer system'19995,906,001'Method and apparatus for performing TLB shutdown operations in a multiprocessor system without invoking interrup handler routines'19995,905,876'Queue ordering for memory and I/O transactions in a multiple concurrent transaction computer system'19995,903,916'Computer memory subsystem and method for performing opportunistic write data transfers during an access latency period within a read or refresh operation'19995,848,279'Mechanism for delivering interrupt messages'19985,829,052'Method and apparatus for managing memory accesses in a multiple multiprocessor cluster system'19985,812,803'Method and apparatus for controlling data transfers between a bus and a memory device using a multi-chip memory controller'19985,796,977'Highly pipelined bus architecture'19985,784,579'Method and apparatus for dynamically controlling bus access from a bus agent based on bus pipeline depth'19985,696,910'Method and apparatus for tracking transactions in a pipelined bus'19975,615,343'Method and apparatus for performing deferred transactions'19975,550,533'High bandwidth self-timed data clocking scheme for memory bus implementation'19965,548,734'Equal length symmetric computer bus topology'19965,537,640'Asynchronous modular bus architecture with cache consistency'19965,513,331'Method and apparatus for automatically configuring system memory address space of a computer system having a memory subsystem with indeterministic number of memory units of indeterministic sizes during system reset'19965,471,637'Method and apparatus for conducting bus transactions between two clock independent bus agents of a computer system using a transaction by transaction deterministic request/response protocol and burst transfer'19955,455,957'Method and apparatus for conducting bus transactions between two clock independent bus agents of a computer system using a transaction by transaction deterministic request/response protocol'19955,301,299'Optimized write protocol for memory accesses utilizing row and column strobes'19945,239,638'Two strobed memory access'1993

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1993–2018Patents assigned to INTEL CORP (57)· patent assignee history
1993–2020Based in Beaverton, OR, US· patent location history
1994Based in Aloha, OR, US· patent location history
2017–2018Patents assigned to PAWLOWSKI STEPHEN S (2)· patent assignee history
2017Patents assigned to BELL DENNIS M (1)· patent assignee history
2018Patents assigned to BRANNOCK KIRK D (1)· patent assignee history
2020Patents assigned to MICRON TECHNOLOGY INC (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
INTEL CORP571993–2018
MICRON TECHNOLOGY INC22020
PAWLOWSKI STEPHEN Sself22017–2018
BELL DENNIS M12017
BRANNOCK KIRK D12018
Locations
LocationPatentsSpan
Beaverton, OR, US591993–2020
Aloha, OR, US11994