Inventor
Mark H. Clark
Inventor
Santa Clara, CA, US
Overview
Patents· 36 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices28%
H10NElectric solid-state devices not otherwise provided for25%
G11CStatic stores11%
H01LSemiconductor devices8%
H10DInorganic electric semiconductor devices6%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%
B82YSpecific uses or applications of nanostructures3%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution3%
PatentTitleYear
10,192,927Semiconductor device for a non-volatile (NV) resistive memory and array structure for an array of NV resistive memory20199,601,690'Sub-oxide interface layer for two-terminal memory'20179,583,701'Methods for fabricating resistive memory device switching material using ion implantation'20179,412,790'Scalable RRAM device architecture for a non-volatile memory device and method'20169,269,897'Device structure for a RRAM and method'20169,252,191'Seed layer for a p+ silicon germanium material for a non-volatile memory device and method'20169,166,163'Sub-oxide interface layer for two-terminal memory'20159,070,859'Low temperature deposition method for polycrystalline silicon material for a non-volatile memory device'20158,946,667'Barrier structure for a silver based RRAM and method'20158,816,315'Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same'20148,809,114'Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same'20148,796,102'Device structure for a RRAM and method'20148,558,220'Memory cell that employs a selectively fabricated carbon nano-tube reversible resistance-switching element formed over a bottom conductor and methods of forming the same'20138,507,315'Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same'20138,501,522'Intermetal stack for use in a photovoltaic cell'20138,467,224'Damascene integration methods for graphitic films in three-dimensional memories and memories formed therefrom'20138,450,835'Reverse leakage reduction and vertical height shrinking of diode with halo doping'20138,450,710'Low temperature p+ silicon junction material for a non-volatile memory device'20138,373,150'Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same'20138,268,678'Diode array and method of making thereof'20128,236,623'Memory cell that employs a selectively fabricated carbon nano-tube reversible resistance-switching element and methods of forming the same'20128,173,486'Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same'20128,102,694'Nonvolatile memory device containing carbon or nitrogen doped diode'20128,072,791'Method of making nonvolatile memory device containing carbon or nitrogen doped diode'20118,049,104'Intermetal stack for use in a photovoltaic cell'20117,994,064'Selective etch for damage at exfoliated surface'20117,977,667'Memory cell that includes a carbon nano-tube reversible resistance-switching element and methods of forming the same'20117,935,594'Damascene process for carbon memory element with MIIM diode'20117,902,537'Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same'20117,897,453'Dual insulating layer diode with asymmetric interface state and method of fabrication'20117,846,782'Diode array and method of making thereof'20107,824,956'Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same'20107,615,439'Damascene process for carbon memory element with MIIM diode'20097,419,701'Low-temperature, low-resistivity heavily doped p-type polysilicon deposition'20086,960,794'Formation of thin channels for TFT devices to ensure low variability of threshold voltages'20056,815,077'Low temperature, low-resistivity heavily doped p-type polysilicon deposition'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2008Based in Upland, CA, US· patent location history
2005Based in Leuven, BE· patent location history
2008–2014Patents assigned to SANDISK 3D LLC (19)· patent assignee history
2009–2019Based in Santa Clara, CA, US· patent location history
2011–2013Patents assigned to CLARK MARK H (9)· patent assignee history
2011–2013Patents assigned to HERNER S BRAD (6)· patent assignee history
2013–2019Patents assigned to CROSSBAR INC (11)· patent assignee history
2013–2016Patents assigned to CLARK MARK HAROLD (5)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SANDISK 3D LLC | 19 | 2008–2014 |
| CROSSBAR INC | 11 | 2013–2019 |
| CLARK MARK Hself | 9 | 2011–2013 |
| HERNER S BRAD | 6 | 2011–2013 |
| CLARK MARK HAROLDself | 5 | 2013–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Santa Clara, California, US | 33 | 2009–2019 |
| Upland, California, US | 2 | 2004–2008 |
| Leuven, BE | 1 | 2005 |