Inventor

William J. Starke

Inventor

Round Rock, TX, US

Overview

1996–2021

Patent span

Physics

Primary field (CPC G)

Patents· 302 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing87%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use6%

H04LTransmission of digital information, e.g. telegraphic communication1%

Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications1%

G11CStatic stores1%

H03MCoding1%

G01RMeasuring electric variables1%

F16FSprings0%

H10DInorganic electric semiconductor devices0%

PatentTitleYear

11,113,204Translation invalidation in a translation cache serving an accelerator2021 11,074,205Managing efficient selection of a particular processor thread for handling an interrupt2021 11,042,325Speculative bank activate dynamic random access memory (DRAM) scheduler2021 11,030,110Integrated circuit and data processing system supporting address aliasing in an accelerator2021 10,846,235Integrated circuit and data processing system supporting attachment of a real address-agnostic accelerator2020 10,831,889Secure memory implementation for secure execution of virtual machines2020 10,824,567Selectively preventing pre-coherence point reads in a cache hierarchy to reduce barrier overhead2020 10,761,995Integrated circuit and data processing system having a configurable cache directory for an accelerator2020 10,664,398Link-level cyclic redundancy check replay for non-blocking coherence flow2020 10,649,853Tracking modifications to a virtual machine image that occur during backup of the virtual machine2020 10,613,940Tracking modifications to a virtual machine image that occur during backup of the virtual machine2020 10,613,792Efficient enforcement of barriers with respect to memory move sequences2020 10,606,777Dropped command truncation for efficient queue utilization in multiprocessor data processing system2020 10,579,527Remote node broadcast of requests in a multinode data processing system2020 10,489,293Information handling system with immediate scheduling of load operations2019 10,474,816Secure memory implementation for secure execution of Virtual Machines2019 10,437,725Master requesting missing segments of a cache line for which the master has coherence ownership2019 10,423,550Managing efficient selection of a particular processor thread for handling an interrupt2019 10,394,711Managing lowest point of coherency (LPC) memory using a service layer adapter2019 10,346,164Memory move instruction sequence targeting an accelerator switchboard2019 10,346,255Method for flagging data modification during a virtual machine backup2019 10,339,009System for flagging data modification during a virtual machine backup2019 10,331,373Migration of memory move instruction sequences between hardware threads2019 10,296,741Secure memory implementation for secure execution of virtual machines2019 10,235,215Memory lock mechanism for a multiprocessor system2019 10,216,653Pre-transmission data reordering for a serial interface2019 10,169,103Managing speculative memory access requests in the presence of transactional storage accesses2019 10,162,755Techniques for implementing barriers to efficiently support cumulativity in a weakly-ordered memory system2018 10,157,134Decreasing the data handoff interval for a reserved cache line based on an early indication of a systemwide coherence response2018 10,152,417Early freeing of a snoop machine of a data processing system prior to completion of snoop processing for an interconnect operation2018 10,152,322Memory move instruction sequence including a stream of copy-type and paste-type instructions2018 10,152,385Virtual machine backup2018 10,140,052Memory access in a data processing system utilizing copy and paste instructions2018 10,133,641Tracking modifications to a virtual machine image that occur during backup of the virtual machine2018 10,126,952Memory move instruction sequence targeting a memory-mapped device2018 10,108,498Virtual machine backup2018 10,108,464Managing speculative memory access requests in the presence of transactional storage accesses2018 10,102,130Decreasing the data handoff interval in a multiprocessor data processing system based on an early indication of a systemwide coherence response2018 10,067,713Efficient enforcement of barriers with respect to memory move sequences2018 9,996,298Memory move instruction sequence enabling software control2018 9,886,350'Tracking modifications to a virtual machine image that occur during backup of the virtual machine'2018 9,880,905'Tracking modifications to a virtual machine image that occur during backup of the virtual machine'2018 9,798,577'Transactional storage accesses supporting differing priority levels'2017 9,792,147'Transactional storage accesses supporting differing priority levels'2017 9,778,933'Non-serialized push instruction for pushing a message payload from a sending thread to a receiving thread'2017 9,766,890'Non-serialized push instruction for pushing a message payload from a sending thread to a receiving thread'2017 9,727,488'Counter-based victim selection in a cache memory'2017 9,727,489'Counter-based victim selection in a cache memory'2017 9,684,551'Addressing for inter-thread push communication'2017 9,678,812'Addressing for inter-thread push communication'2017 9,619,390'Proactive prefetch throttling'2017 9,575,825'Push instruction for pushing a message payload from a sending thread to a receiving thread'2017 9,569,293'Push instruction for pushing a message payload from a sending thread to a receiving thread'2017 9,563,558'Techniques for implementing barriers to efficiently support cumulativity in a weakly-ordered memory system'2017 9,519,502'Virtual machine backup'2016 9,514,045'Techniques for implementing barriers to efficiently support cumulativity in a weakly-ordered memory system'2016 9,514,049'Cache backing store for transactional memory'2016 9,501,411'Cache backing store for transactional memory'2016 9,495,312'Determining command rate based on dropped commands'2016 9,495,314'Determining command rate based on dropped commands'2016 9,471,410'Transient condition management utilizing a posted error detection processing protocol'2016 9,454,484'Integrated circuit system having decoupled logical and physical interfaces'2016 9,442,852'Programmable coherent proxy for attached processor'2016 9,367,504'Coherency overcommit'2016 9,367,458'Programmable coherent proxy for attached processor'2016 9,367,505'Coherency overcommit'2016 9,355,035'Dynamic write priority based on virtual write queue high water mark for set associative cache using cache cleaner when modified sets exceed threshold'2016 9,342,387'Hardware-assisted interthread push communication'2016 9,336,145'Techniques for cache injection in a processor system based on a shared state'2016 9,286,148'Hardware-assisted interthread push communication'2016 9,280,465'Techniques for moving checkpoint-based high-availability log and data directly from a producer cache to a consumer cache'2016 9,274,952'Moving checkpoint-based high-availability log and data directly from a producer cache to a consumer cache'2016 9,274,856'Improving processor performance for instruction sequences that include barrier instructions'2016 9,268,703'Techniques for cache injection in a processor system from a remote node'2016 9,231,618'Early data tag to allow data CRC bypass via a speculative memory data return protocol'2016 9,189,403'Selective cache-to-cache lateral castouts'2015 9,176,876'Selective cache-to-cache lateral castouts'2015 9,110,808'Formation of an exclusive ownership coherence state in a lower level cache upon replacement from an upper level cache of a cache line in a private shared owner state'2015 9,106,258'Early data tag to allow data CRC bypass via a speculative memory data return protocol'2015 9,086,975'Coherent proxy for attached processor'2015 9,069,701'Virtual machine failover'2015 9,069,674'Coherent proxy for attached processor'2015 9,058,195'Virtual machines failover'2015 9,058,178'Selective posted data error detection based on request type'2015 9,058,260'Transient condition management utilizing a posted error detection processing protocol'2015 9,047,221'Virtual machines failover'2015 9,032,157'Virtual machine failover'2015 8,990,640'Selective posted data error detection based on request type'2015 8,959,289'Data cache block deallocate requests'2015 8,935,513'Processor performance improvement for instruction sequences that include barrier instructions'2015 8,930,629'Data cache block deallocate requests in a multi-level cache hierarchy'2015 8,893,126'Binding a process to a special purpose processing element having characteristics of a processor'2014 8,874,852'Data cache block deallocate requests in a multi-level cache hierarchy'2014 8,856,455'Data cache block deallocate requests'2014 8,838,901'Coordinated writeback of dirty cachelines'2014 8,683,128'Memory bus write prioritization'2014 8,683,140'Cache-based speculation of stores following synchronizing operations'2014 8,656,128'Aggregate data processing system having multiple overlapping synthetic computers'2014 8,656,129'Aggregate symmetric multiprocessor system'2014 8,656,121'Facilitating data coherency using in-memory tag bits and tag test instructions'2014 8,645,633'Facilitating data coherency using in-memory tag bits and faulting stores'2014 8,645,644'Facilitating data coherency using in-memory tag bits and tag test instructions'2014 8,645,627'Memory bus write prioritization'2014 8,615,634'Coordinated writeback of dirty cachelines'2013 8,521,982'Load request scheduling in a cache hierarchy'2013 8,510,512'Memory coherence directory supporting remotely sourced requests of nodal scope'2013 8,504,779'Memory coherence directory supporting remotely sourced requests of nodal scope'2013 8,499,124'Handling castout cache lines in a victim cache'2013 8,495,308'Processor, data processing system and method supporting a shared global coherency state'2013 8,489,819'Victim cache lateral castout targeting'2013 8,484,307'Host fabric interface (HFI) to perform global shared memory (GSM) operations'2013 8,433,851'Reducing wiring congestion in a cache subsystem utilizing sectored caches with discontiguous addressing'2013 8,412,888'Cache-based speculation of stores following synchronizing operations'2013 8,370,595'Aggregate data processing system having multiple overlapping synthetic computers'2013 8,364,922'Aggregate symmetric multiprocessor system'2013 8,347,036'Empirically based dynamic control of transmission of victim cache lateral castouts'2013 8,347,037'Victim cache replacement'2013 8,332,588'Performing a partial cache line storage-modifying operation based upon a hint'2012 8,327,074'Synchronizing access to data in shared memory via upper level cache queuing'2012 8,327,073'Empirically based dynamic control of acceptance of victim cache lateral castouts'2012 8,327,072'Victim cache replacement'2012 8,312,220'Mode-based castout destination selection'2012 8,296,519'Synchronizing access to data in shared memory via upper level cache queuing'2012 8,281,075'Processor system and methods of triggering a block move using a system bus write command initiated by user code'2012 8,254,411'Data processing system, method and interconnect fabric having a flow governor'2012 8,230,178'Data processing system and method for efficient coherency communication utilizing coherency domain indicators'2012 8,230,117'Techniques for write-after-write ordering in a coherency managed processor system that employs a command pipeline'2012 8,225,045'Lateral cache-to-cache cast-in'2012 8,214,600'Data processing system and method for efficient coherency communication utilizing coherency domains'2012 8,214,603'Method and apparatus for handling multiple memory requests within a multiprocessor system'2012 8,214,592'Dynamic runtime modification of array layout for offset'2012 8,209,489'Victim cache prefetching'2012 8,205,024'Protecting ownership transfer with non-uniform protection windows'2012 8,205,136'Fault tolerant encoding of directory states for stuck bits'2012 8,195,880'Information handling system with immediate scheduling of load operations in a dual-bank cache with dual dispatch into write/read data flow'2012 8,166,246'Chaining multiple smaller store queue entries for more efficient store queue usage'2012 8,140,765'Information handling system with immediate scheduling of load operations in a dual-bank cache with single dispatch into write/read data flow'2012 8,140,771'Partial cache line storage-modifying operation based upon a hint'2012 8,139,592'Ticket-based operation tracking'2012 8,140,759'Specifying an access hint for prefetching partial cache block data in a cache hierarchy'2012 8,140,756'Information handling system with immediate scheduling of load operations and fine-grained access to cache memory'2012 8,140,770'Data processing system and method for predictively selecting a scope of broadcast of an operation'2012 8,135,910'Bandwidth of a cache directory by slicing the cache directory into two smaller cache directories and replicating snooping logic for each sliced cache directory'2012 8,131,935'Virtual barrier synchronization cache'2012 8,117,397'Victim cache line selection'2012 8,117,390'Updating partial cache lines in a data processing system'2012 8,103,791'Synchronized communication in a data processing system'2012 8,099,570'Methods, systems, and computer program products for dynamic selective memory mirroring'2012 8,095,733'Virtual barrier synchronization cache castout election'2012 8,015,358'System bus structure for large L2 cache array topology with different latency domains'2011 8,001,330'L2 cache controller with slice directory and unified cache structure'2011 7,996,564'Remote asynchronous data mover'2011 7,992,051'Method, apparatus, and computer program product in a processor for dynamically during runtime allocating memory for in-memory hardware tracing'2011 7,987,320'Cache mechanism and method for avoiding cast out on bad victim select and recycling victim select operation'2011 7,966,454'Issuing global shared memory operations via direct cache injection to a host fabric interface'2011 7,944,932'Interconnect fabric for a data processing system'2011 7,941,611'Filtering snooped operations'2011 7,925,842'Allocating a global shared memory'2011 7,917,730'Processor chip with multiple computing elements and external i/o interfaces connected to perpendicular interconnection trunks communicating coherency signals via intersection bus controller'2011 7,913,123'Concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers'2011 7,890,704'Implementing an enhanced hover state with active prefetches'2011 7,865,650'Processor with coherent bus controller at perpendicularly intersecting axial bus layout for communication among SMP compute elements and off-chip I/O elements'2011 7,849,298'Enhanced processor virtualization mechanism via saving and restoring soft processor/system states'2010 7,844,860'Apparatus and computer program product in a processor for performing in-memory tracing using existing communication paths'2010 7,831,774'Pipelining D states for MRU steerage during MRU-LRU member allocation'2010 7,827,354'Victim cache using direct intervention'2010 7,818,388'Data processing system, method and interconnect fabric supporting multiple planes of processing nodes'2010 7,818,511'Reducing number of rejected snoop requests by extending time to respond to snoop request'2010 7,793,048'System bus structure for large L2 cache array topology with different latency domains'2010 7,783,841'Efficient coherency communication utilizing an IG coherency state'2010 7,783,842'Cache coherent I/O communication'2010 7,783,834'L2 cache array topology for large cache with different latency domains'2010 7,774,555'Data processing system and method for efficient coherency communication utilizing coherency domain indicators'2010 7,761,631'Data processing system, method and interconnect fabric supporting destination data tagging'2010 7,747,826'Data processing system and method for efficient communication utilizing an in coherency state'2010 7,743,218'Updating an invalid coherency state in response to snooping an operation'2010 7,734,876'Protecting ownership transfer with non-uniform protection windows'2010 7,725,619'Data processing system and method that permit pipelining of I/O write operations and multiple operation scopes'2010 7,716,428'Data processing system, cache system and method for reducing imprecise invalid coherency states'2010 7,716,427'Store stream prefetching in a microprocessor'2010 7,689,891'Method and system for handling stuck bits in cache directories'2010 7,689,771'Coherency management of castouts'2010 7,689,777'Cache member protection with partial make MRU allocation'2010 7,627,738'Request and combined response broadcasting to processors coupled to other processors within node and coupled to respective processors in another node'2009 7,610,458'Data processing system, processor and method of data processing that support memory access according to diverse memory models'2009 7,584,331'Data processing system and method for selectively updating an invalid coherency state in response to snooping a castout'2009 7,584,329'Data processing system and method for efficient communication utilizing an Ig coherency state'2009 7,577,797'Data processing system, cache system and method for precisely forming an invalid coherency state based upon a combined response'2009 7,543,116'Data processing system, cache system and method for handling a flush operation in a data processing system having multiple coherency domains'2009 7,536,513'Data processing system, cache system and method for issuing a request on an interconnect fabric without reference to a lower level cache based upon a tagged cache state'2009 7,533,321'Fault tolerant encoding of directory states for stuck bits'2009 7,523,268'Reducing number of rejected snoop requests by extending time to respond to snoop request'2009 7,512,742'Data processing system, cache system and method for precisely forming an invalid coherency state indicating a broadcast scope'2009 7,500,065'Data processing system and method for efficient L3 cache directory management'2009 7,493,478'Enhanced processor virtualization mechanism via saving and restoring soft processor/system states'2009 7,490,202'Data processing system and method for efficient L3 cache directory management'2009 7,490,200'L2 cache controller with slice directory and unified cache structure'2009 7,484,042'Data processing system and method for predictively selecting a scope of a prefetch operation'2009 7,484,046'Reducing number of rejected snoop requests by extending time to respond to snoop request'2009 7,483,422'Data processing system, method and interconnect fabric for selective link information allocation in a data processing system'2009 7,480,772'Data processing system and method for efficient communication utilizing an Tn and Ten coherency states'2009 7,478,201'Data processing system, cache system and method for passively scrubbing a domain indication'2009 7,475,196'Processor, data processing system, and method for initializing a memory block in a data processing system having multiple coherency domains'2009 7,475,195'Data processing system, cache system and method for actively scrubbing a domain indication'2009 7,469,318'System bus structure for large L2 cache array topology with different latency domains'2008 7,467,262'Data processing system, cache system and method for scrubbing a domain indication in response to execution of program code'2008 7,454,580'Data processing system, processor and method of data processing that reduce store queue entry utilization for synchronizing operations'2008 7,454,577'Data processing system and method for efficient communication utilizing an Tn and Ten coherency states'2008 7,454,578'Data processing system and method for predictively selecting a scope of broadcast of an operation utilizing a location of a memory'2008 7,451,231'Data processing system, method and interconnect fabric for synchronized communication in a data processing system'2008 7,451,277'Data processing system, cache system and method for updating an invalid coherency state in response to snooping an operation'2008 7,447,844'Data processing system, processor and method of data processing in which local memory access requests are serviced on a fixed schedule'2008 7,447,845'Data processing system, processor and method of data processing in which local memory access requests are serviced by state machines with differing functionality'2008 7,444,494'Data processing system and method for predictively selecting a scope of broadcast of an operation utilizing a history-based prediction'2008 7,437,618'Method in a processor for dynamically during runtime allocating memory for in-memory hardware tracing'2008 7,437,617'Method, apparatus, and computer program product in a processor for concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers'2008 7,421,619'Method in a processor for performing in-memory tracing using existing communication paths'2008 7,409,481'Data processing system, method and interconnect fabric supporting destination data tagging'2008 7,404,046'Cache memory, processing unit, data processing system and method for filtering snooped operations'2008 7,401,189'Pipelining D states for MRU steerage during MRU/LRU member allocation'2008 7,389,388'Data processing system and method for efficient communication utilizing an in coherency state'2008 7,386,682'Reducing number of rejected snoop requests by extending time to respond to snoop request'2008 7,386,681'Reducing number of rejected snoop requests by extending time to respond to snoop request'2008 7,380,102'Communication link control among inter-coupled multiple processing units in a node to respective units in another node for request broadcasting and combined response'2008 7,380,066'Store stream prefetching in a microprocessor'2008 7,366,841'L2 cache array topology for large cache with different latency domains'2008 7,363,433'Cache member protection with partial make MRU allocation'2008 7,343,455'Cache mechanism and method for avoiding cast out on bad victim select and recycling victim select operation'2008 7,340,568'Reducing number of rejected snoop requests by extending time to respond to snoop request'2008 7,337,280'Data processing system and method for efficient L3 cache directory management'2008 7,308,537'Half-good mode for large L2 cache array topology with different latency domains'2007 7,305,522'Victim cache using direct intervention'2007 7,305,523'Cache memory direct intervention'2007 7,284,102'System and method of re-ordering store operations within a processor'2007 7,272,664'Cross partition sharing of state information'2007 7,272,773'Cache directory array recovery mechanism to support special ECC stuck bit matrix'2007 7,254,694'Processors interconnect fabric with relay broadcasting and accumulation of partial responses'2007 7,237,070'Cache memory, processing unit, data processing system and method for assuming a selected invalid coherency state based upon a request source'2007 7,228,385'Processor, data processing system and method for synchronizing access to data in shared memory'2007 7,200,717'Processor, data processing system and method for synchronizing access to data in shared memory'2007 7,197,604'Processor, data processing system and method for synchronzing access to data in shared memory'2007 7,117,319'Managing processor architected state upon an interrupt'2006 7,103,721'Cache allocation mechanism for biasing subsequent allocations based upon cache directory state'2006 7,069,494'Application of special ECC matrix for solving stuck bit faults in an ECC protected mechanism'2006 7,047,320'Data processing system providing hardware acceleration of input/output (I/O) communication'2006 7,039,832'Robust system reliability via systolic manufacturing level chip test operating real time on microprocessors/systems'2006 7,039,760'Programming means for dynamic specifications of cache management preferences'2006 7,032,097'Zero cycle penalty in selecting instructions in prefetch buffer in the event of a miss in the instruction cache'2006 6,996,679'Cache allocation mechanism for saving multiple elected unworthy members via substitute victimization and imputed worthiness of multiple substitute victim members'2006 6,993,628'Cache allocation mechanism for saving elected unworthy member via substitute victimization and imputed worthiness of substitute victim member'2006 6,983,347'Dynamically managing saved processor soft states'2006 6,981,083'Processor virtualization mechanism via an enhanced restoration of hard architected states'2005 6,976,148'Acceleration of input/output (I/O) communication through improved address translation'2005 6,877,083'Address mapping mechanism for behavioral memory enablement within a data processing system'2005 6,848,044'Circuits and methods for recovering link stack data upon branch instruction mis-speculation'2005 6,804,770'Method and apparatus for using past history to avoid flush conditions in a microprocessor'2004 6,792,521'Behavioral memory mechanism for a data processing system'2004 6,785,774'High performance symmetric multiprocessing systems via super-coherent data mechanisms'2004 6,779,086'Symmetric multiprocessor systems with an independent super-coherent cache directory'2004 6,763,435'Super-coherent multiprocessor system bus protocols'2004 6,704,844'Dynamic hardware and software performance optimizations for super-coherent SMP systems'2004 6,694,427'Method system and apparatus for instruction tracing with out of order processors'2004 6,681,321'Method system and apparatus for instruction execution tracing with out of order processors'2004 6,678,814'Method and apparatus for allocating data usages within an embedded dynamic random access memory device'2004 6,675,279'Behavioral memory enabled fetch prediction mechanism within a data processing system'2004 6,658,539'Super-coherent data mechanisms for shared caches in a multiprocessing system'2003 6,651,162'Recursively accessing a branch target address cache using a target address previously accessed from the branch target address cache'2003 6,643,763'Register pipe for multi-processing engine environment'2003 6,629,212'High speed lock acquisition mechanism with time parameterized cache coherency states'2003 6,629,209'Cache coherency protocol permitting sharing of a locked data granule'2003 6,629,214'Extended cache coherency protocol with a persistent lock acquired state'2003 6,625,701'Extended cache coherency protocol with a modified store instruction lock release indicator'2003 6,606,666'Method and system for controlling information flow between a producer and a buffer in a high frequency digital system'2003 6,606,680'Method and apparatus for accessing banked embedded dynamic random access memory devices'2003 6,604,145'Method and system for controlling information flow in a high frequency digital system from a producer to a buffering consumer via an intermediate buffer and a shared data path'2003 6,601,105'Method and system for controlling information flow between a producer and multiple buffers in a high frequency digital system'2003 6,598,086'Method and system for controlling information flow in a high frequency digital system from a producer to a buffering consumer via an intermediate buffer'2003 6,574,719'Method and apparatus for concurrently communicating with multiple embedded dynamic random access memory devices'2003 6,549,989'Extended cache coherency protocol with a lock released state'2003 6,493,814'Reducing resource collisions associated with memory units in a multi-level hierarchy memory system'2002 6,487,637'Method and system for clearing dependent speculations from a request queue'2002 6,438,656'Method and system for cancelling speculative cache prefetch requests'2002 6,430,656'Cache and management method using combined software and hardware congruence class selectors'2002 6,421,761'Partitioned cache and management method for selectively caching data by type'2002 6,418,516'Method and system for managing speculative requests in a multi-level memory hierarchy'2002 6,385,702'High performance multiprocessor system with exclusive-deallocate cache state'2002 6,374,333'Cache coherency protocol in which a load instruction hint bit is employed to indicate deallocation of a modified cache line supplied by intervention'2002 6,349,369'Protocol for transferring modified-unsolicited state during data intervention'2002 6,345,342'Cache coherency protocol employing a read operation including a programmable flag to indicate deallocation of an intervened cache line'2002 6,345,344'Cache allocation mechanism for modified-unsolicited cache state that modifies victimization priority bits'2002 6,345,343'Multiprocessor system bus protocol with command and snoop responses for modified-unsolicited cache state'2002 6,321,306'High performance multiprocessor system with modified-unsolicited cache state'2001 6,314,498'Multiprocessor system bus transaction for transferring exclusive-deallocate cache state to lower lever cache'2001 6,075,937'Preprocessing of stored target routines for controlling emulation of incompatible instructions on a target processor and utilizing target processor feedback for controlling non-sequential incompatible instruction emulation'2000 6,009,261'Preprocessing of stored target routines for emulating incompatible instructions on a target processor'1999 5,894,575'Method and system for initial state determination for instruction trace reconstruction'1999 5,889,947'Apparatus and method for executing instructions that select a storage location for output values in response to an operation count'1999 5,878,208'Method and system for instruction trace reconstruction utilizing limited output pins and bus monitoring'1999 5,862,371'Method and system for instruction trace reconstruction utilizing performance monitor outputs and bus monitoring'1999 5,809,566'Automatic cache prefetch timing with dynamic trigger migration'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1996–2021Patents assigned to IBM (298)· patent assignee history

1996–2016Based in Austin, TX, US· patent location history

2002–2021Based in Round Rock, TX, US· patent location history

2012–2019Patents assigned to STARKE WILLIAM J (55)· patent assignee history

2012–2019Patents assigned to GUTHRIE GUY L (44)· patent assignee history

2012–2017Patents assigned to WILLIAMS DEREK E (29)· patent assignee history

2012–2015Patents assigned to STUECHELI JEFFREY A (15)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	298	1996–2021
STARKE WILLIAM Jself	55	2012–2019
GUTHRIE GUY L	44	2012–2019
WILLIAMS DEREK E	29	2012–2017
STUECHELI JEFFREY A	15	2012–2015

Locations

Location	Patents	Span
Round Rock, Texas, US	264	2002–2021
Austin, Texas, US	38	1996–2016