LexDanaLexDanabeta
Inventor

Ashish Singhai

Inventor
Cupertino, CA, US

Overview

50→
Patents
1999–2021
Patent span
Physics
Primary field (CPC G)

Patents· 50 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing58%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use20%
G11CStatic stores8%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications6%
H03MCoding5%
H04LTransmission of digital information, e.g. telegraphic communication3%
PatentTitleYear
11,132,255Methods and systems for implementing redundancy in memory controllers202110,915,247Efficient data management through compressed data interfaces202110,809,928Efficient data deduplication leveraging sequential chunks or auxiliary databases202010,691,531Systems and methods for multi-zone data tiering for endurance extension in solid state drives202010,628,260Methods and systems for implementing redundancy in memory controllers202010,572,153Efficient data management through compressed data interfaces202010,565,057Indirection-based storage system backups using markers including sets of serial numbers associated with segments202010,445,208Tunable, efficient monitoring of capacity usage in distributed storage systems201910,353,813Checkpoint based technique for bootstrapping forward map under constrained memory for flash devices201910,275,376Efficient cross device redundancy implementation on high performance direct attached non-volatile storage with data reduction201910,152,389Apparatus and method for inline compression and deduplication201810,133,629Methods and systems for implementing redundancy in memory controllers201810,108,340Method and system for a common processing framework for memory device controllers201810,089,360Apparatus and method for single pass entropy detection on data transfer201810,073,626Managing the write performance of an asymmetric memory system201810,067,823Systems and methods for adaptive error corrective code mechanisms20189,898,196'Small block write operations in non-volatile memory systems'20189,886,196'Method and system for efficient common processing in memory device controllers'20189,842,660'System and method to improve enterprise reliability through tracking I/O performance metrics in non-volatile random access memory'20179,836,409Seamless application access to hybrid main memory20179,733,840'Managing the write performance of an asymmetric memory system'20179,727,452'Distributing metadata across multiple different disruption regions within an asymmetric memory system'20179,678,665'Methods and systems for memory page allocation'20179,672,158'Asymmetric memory migration in hybrid main memory'20179,619,326'Methods and systems for implementing redundancy in memory controllers'20179,588,698'Managing the write performance of an asymmetric memory system'20179,575,669'Programmable solid state drive controller and method for scheduling commands utilizing a data structure'20179,552,384'Apparatus and method for single pass entropy detection on data transfer'20179,477,595'Managing the write performance of an asymmetric memory system'20169,323,663'Managing the write performance of an asymmetric memory system'20169,304,908'Small block write operations in non-volatile memory systems'20169,262,333'Asymmetric memory migration in hybrid main memory'20169,262,334'Seamless application access to hybrid main memory'20169,223,719'Integrating data from symmetric and asymmetric memory'20159,164,891'Managing the write performance of an asymmetric memory system'20159,021,188'Small block write operations in non-volatile memory systems'20158,996,796'Small block write operations in non-volatile memory systems'20158,782,373'Seamless application access to hybrid main memory'20148,639,910'Handling writes to a memory including asymmetric and symmetric components'20148,555,002'Asymmetric memory migration in hybrid main memory'20138,555,024'Integrating data from symmetric and asymmetric memory'20138,266,407'Writing to asymmetric memory'20128,205,061'Seamless application access to hybrid main memory'20128,156,288'Asymmetric memory migration in hybrid main memory'20128,156,302'Integrating data from symmetric and asymmetric memory'20127,930,513'Writing to asymmetric memory'20117,913,055'Seamless application access to hybrid main memory'20117,818,489'Integrating data from symmetric and asymmetric memory'20107,774,556'Asymmetric memory migration in hybrid main memory'20105,938,732'Load balancing and failover of network services'1999

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1999Based in Urbana, IL, US· patent location history
2010–2018Patents assigned to VIRIDENT SYSTEMS INC (26)· patent assignee history
2010–2018Based in Cupertino, CA, US· patent location history
2012–2017Patents assigned to KARAMCHETI VIJAY (9)· patent assignee history
2012–2017Patents assigned to SINGHAI ASHISH (9)· patent assignee history
2012–2014Patents assigned to GANAPATHY KUMAR (8)· patent assignee history
2017–2021Patents assigned to WESTERN DIGITAL TECH INC (18)· patent assignee history
2017–2021Based in Los Altos, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
VIRIDENT SYSTEMS INC262010–2018
WESTERN DIGITAL TECH INC182017–2021
KARAMCHETI VIJAY92012–2017
SINGHAI ASHISHself92012–2017
GANAPATHY KUMAR82012–2014
Locations
LocationPatentsSpan
Cupertino, California, US282010–2018
Los Altos, California, US212017–2021
Urbana, Illinois, US11999