Inventor
Kuo-Chi Tu
Inventor
Hsinchu, TW
Overview
Patents· 151 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices27%
H01LSemiconductor devices20%
H10DInorganic electric semiconductor devices18%
H10NElectric solid-state devices not otherwise provided for15%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
G11CStatic stores6%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h104%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%
H01GCapacitors0%
PatentTitleYear
11,094,744Interconnect landing method for RRAM technology202111,088,2033D RRAM cell structure for reducing forming and set voltages202111,037,941Method for forming an integrated circuit and an integrated circuit202111,017,852Method of forming memory device202111,011,224Memory device and method for forming the same202111,004,975Semiconductor device and manufacturing method thereof202110,950,784RRAM with a barrier layer202110,930,333Embedded ferroelectric memory cell202110,903,274Interconnect landing method for RRAM technology202110,879,391Wakeup-free ferroelectric memory device202010,868,250Resistance variable memory structure and method of forming the same202010,862,029Top electrode for device structures in interconnect202010,847,606Capacitor and method for making same202010,796,759Method and apparatus for reading RRAM cell202010,763,270Method for forming an integrated circuit and an integrated circuit202010,749,108Logic compatible RRAM structure and process202010,727,337Semiconductor device and manufacturing method thereof202010,700,275RRAM cell structure with laterally offset BEVA/TEVA202010,622,300Series MIM structures202010,566,387Interconnect landing method for RRAM technology202010,510,953Top electrode for device structures in interconnect201910,497,436Memory device and fabrication thereof201910,475,852Resistive switching random access memory with asymmetric source and drain201910,388,868Resistance variable memory structure and method of forming the same201910,311,952Method and apparatus for reading RRAM cell201910,276,489Series MIM structures201910,276,790Top electrode for device structures in interconnect201910,249,756Semiconductor device including memory and logic circuit having FETs with ferroelectric layer and manufacturing methods thereof201910,199,575RRAM cell structure with laterally offset BEVA/TEVA201910,164,094Semiconductor device including memory and logic circuit having FETs with ferroelectric layer and manufacturing methods thereof201810,164,185RRAM cell with PMOS access transistor201810,163,981Metal landing method for RRAM technology201810,157,976Capacitor and method for making same201810,158,072Step height reduction of memory element201810,158,070Logic compatible RRAM structure and process201810,103,200Resistive switching random access memory with asymmetric source and drain201810,103,330Resistance variable memory structure201810,050,197Resistance variable memory structure201810,038,139One transistor and one resistive random access memory (RRAM) structure with spacer201810,008,662Perpendicular magnetic tunneling junction (MTJ) for improved magnetoresistive random-access memory (MRAM) process20189,985,203Resistive random access memory (RRAM) with improved forming voltage characteristics and method for making20189,947,617Series MIM structures20189,941,470RRAM device with data storage layer having increased height20189,934,853Method and apparatus for reading RRAM cell20189,853,213Logic compatible RRAM structure and process20179,847,480Resistance variable memory structure and method of forming the same20179,818,938'Method of forming a semiconductor structure'20179,780,302'Top electrode for device structures in interconnect'20179,780,145'Resistive random access memory (RRAM) structure'20179,773,552'RRAM cell with PMOS access transistor'20179,679,960'Semiconductor devices, methods of manufacture thereof, and methods of manufacturing capacitors'20179,673,391'Resistance variable memory structure and method of forming the same'20179,614,025'Method of fabricating semiconductor device'20179,601,545'Series MIM structures compatible with RRAM process'20179,583,556'Process-compatible decoupling capacitor and method for making the same'20179,577,009'RRAM cell with PMOS access transistor'20179,553,265'RRAM device with data storage layer having increased height'20179,553,095'Capacitor and method for making same'20179,537,094'Logic compatible RRAM structure and process'20179,478,638'Resistive switching random access memory with asymmetric source and drain'20169,466,794'Low form voltage resistive random access memory (RRAM)'20169,444,045'Top electrode for device structures in interconnect'20169,431,604'Resistive random access memory (RRAM) and method of making'20169,425,392'RRAM cell structure with laterally offset BEVA/TEVA'20169,401,395'Decoupling MIM capacitor designs for interposers and methods of manufacture thereof'20169,368,722'Resistive random access memory and manufacturing method thereof'20169,368,567'Semiconductor devices, methods of manufacture thereof, and methods of manufacturing capacitors'20169,356,072'Resistive random access memory (RRAM) structure'20169,349,953'Resistance variable memory structure and method of forming the same'20169,331,277'One transistor and one resistive random access memory (RRAM) structure with spacer'20169,312,482'Resistance variable memory structure and method of forming the same'20169,269,760'Method of fabricating semiconductor device'20169,269,762'Metal-insulator-metal (MIM) capacitor within topmost thick inter-metal dielectric layers'20169,263,415'Decoupling MIM capacitor designs for interposers and methods of manufacture thereof'20169,257,409'Decoupling MIM capacitor designs for interposers and methods of manufacture thereof'20169,236,570'Resistive memory cell array with top electrode bit line'20169,231,197'Logic compatible RRAM structure and process'20169,231,205'Low form voltage resistive random access memory (RRAM)'20169,172,036'Top electrode blocking layer for RRAM device'20159,130,162'Resistance variable memory structure and method of forming the same'20159,112,148'RRAM cell structure with laterally offset BEVA/TEVA'20159,099,647'One transistor and one resistive (1T1R) random access memory (RAM) structure with dual spacers'20159,076,522'Memory cells breakdown protection'20159,048,212'Semiconductor devices, methods of manufacture thereof, and methods of manufacturing capacitors'20159,023,699'Resistive random access memory (RRAM) structure and method of making the RRAM structure'20158,994,146'Metal-insulator-metal (MIM) capacitor within topmost thick inter-metal dielectric layers'20158,993,405'Method of fabricating metal-insulator-metal (MIM) capacitor within topmost thick inter-metal dielectric layers'20158,987,086'MIM capacitor with lower electrode extending through a conductive layer to an STI'20158,969,937'Semiconductor device'20158,963,114'One transistor and one resistive (1T1R) random access memory (RRAM) structure with dual spacers'20158,952,347'Resistive memory cell array with top electrode bit line'20158,921,818'Resistance variable memory structure'20148,908,415'Resistive memory reset'20148,896,096'Process-compatible decoupling capacitor and method for making the same'20148,871,604'Methods of manufacturing semiconductor devices that include forming a capacitor using a cap layer'20148,853,762'Structure for protecting metal-insulator-metal capacitor in memory device from charge damage'20148,759,193'Method of fabricating semiconductor device'20148,748,284'Method of manufacturing decoupling MIM capacitor designs for interposers'20148,742,390'Logic compatible RRAM structure and process'20148,716,100'Method of fabricating metal-insulator-metal (MIM) capacitor within topmost thick inter-metal dielectric layers'20148,659,121'Semiconductor devices with orientation-free decoupling capacitors and methods of manufacture thereof'20148,643,074'Semiconductor device'20148,617,949'Capacitor and method for making same'20138,604,531'Method and apparatus for improving capacitor capacitance and compatibility'20138,487,361'Devices and methods for preventing capacitor leakage'20138,436,408'Semiconductor device with decoupling capacitor design'20138,242,551'Metal-insulator-metal structure for system-on-chip technology'20128,232,587'Method of forming a metal-insulator-metal capacitor'20128,143,699'Dual-dielectric MIM capacitors for system-on-chip applications'20128,012,836'Semiconductor devices and methods for fabricating the same'20117,884,408'One-transistor random access memory technology compatible with metal gate process'20117,851,861'MIM capacitor and metal gate transistor'20107,745,865'Devices and methods for preventing capacitor leakage'20107,666,737'Method of forming a metal-insulator-metal capacitor'20107,557,399'Metal-insulator-metal capacitors'20097,381,613'Self-aligned MIM capacitor process for embedded DRAM'20087,382,012'Reducing parasitic capacitance of MIM capacitor in integrated circuits by reducing effective dielectric constant of dielectric layer'20087,355,240'Semiconductor product including logic, non-volatile memory and volatile memory devices and method for fabrication thereof'20087,329,953'Structure for reducing leakage currents and high contact resistance for embedded memory and method for making same'20087,282,757'MIM capacitor structure and method of manufacture'20077,271,083'One-transistor random access memory technology compatible with metal gate process'20077,262,090'Random access memory (RAM) capacitor in shallow trench isolation with improved electrical isolation to overlying gate electrodes'20077,199,423'Non-volatile memory technology compatible with 1T-RAM process'20077,195,970'Metal-insulator-metal capacitors'20077,189,613'Method and structure for metal-insulator-metal capacitor based memory device'20077,163,853'Method of manufacturing a capacitor and a metal gate on a semiconductor device'20077,115,935'Embedded DRAM for metal-insulator-metal (MIM) capacitor structure'20067,071,509'Method of improving the top plate electrode stress inducting voids for 1T-RAM process'20067,029,968'Method of forming a PIP capacitor'20067,030,444'Space process to prevent the reverse tunneling in split gate flash'20067,019,348'Embedded semiconductor product with dual depth isolation regions'20066,949,785'Random access memory (RAM) capacitor in shallow trench isolation with improved electrical isolation to overlying gate electrodes'20056,902,975'Non-volatile memory technology compatible with 1T-RAM process'20056,872,622'Method of forming a capacitor top plate structure to increase capacitance and to improve top plate to bit line overlay margin'20056,867,129'Method of improving the top plate electrode stress inducting voids for 1T-RAM process'20056,853,024'Self-aligned MIM capacitor process for embedded DRAM'20056,833,578'Method and structure improving isolation between memory cell passing gate and capacitor'20046,812,093'Method for fabricating memory cell structure employing contiguous gate and capacitor dielectric layer'20046,764,967'Method for forming low thermal budget sacrificial oxides'20046,734,526'Oxidation resistant microelectronics capacitor structure with L shaped isolation spacer'20046,720,232'Method of fabricating an embedded DRAM for metal-insulator-metal (MIM) capacitor structure'20046,709,919'Method for making auto-self-aligned top electrodes for DRAM capacitors with improved capacitor-to-bit-line-contact overlay margin'20046,682,982'Process method for 1T-SRAM'20046,642,097'Structure for capacitor-top-plate to bit-line-contact overlay margin'20036,627,493'Self-aligned method for fabricating a capacitor under bit-line (cub) dynamic random access memory (DRAM) cell structure'20036,602,749'Capacitor under bitline (CUB) memory cell structure with reduced parasitic capacitance'20036,503,796'Method and structure for a top plate design for making capacitor-top-plate to bit-line-contact overlay margin'20036,486,033'SAC method for embedded DRAM devices'20026,300,191'Method of fabricating a capacitor under bit line structure for a dynamic random access memory device'20016,294,426'Method of fabricating a capacitor under bit line structure with increased capacitance without increasing the aspect ratio for a dry etched bit line contact hole'20016,200,898'Global planarization process for high step DRAM devices via use of HF vapor etching'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (81)· patent assignee history
2001–2021Based in Hsinchu, TW· patent location history
2012–2015Patents assigned to TU KUO-CHI (16)· patent assignee history
2012–2015Patents assigned to CHING KUO-CHENG (4)· patent assignee history
2013–2014Patents assigned to WANG CHEN-JONG (4)· patent assignee history
2015–2021Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (67)· patent assignee history
2021Based in Hsin Chu, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG | 81 | 2001–2016 |
| TAIWAN SEMICONDUCTOR MFG CO LTD | 67 | 2015–2021 |
| TU KUO-CHIself | 16 | 2012–2015 |
| CHING KUO-CHENG | 4 | 2012–2015 |
| WANG CHEN-JONG | 4 | 2013–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 149 | 2001–2021 |
| Hsin Chu, TW | 2 | 2021 |