Inventor
Jung-Sheng Hoei
Inventor
Newark, CA, US
Overview
Patents· 107 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores63%
G06FElectric digital data processing23%
H01LSemiconductor devices3%
H10BElectronic memory devices3%
H03FAmplifiers1%
H10DInorganic electric semiconductor devices1%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use1%
Y10TTechnical subjects covered by former us classification1%
H03GControl of amplification1%
H03HImpedance networks, e.g. resonant circuits1%
PatentTitleYear
11,132,303Memory sub-system management of firmware block record and device block record202111,081,189Charge loss compensation202111,061,578Monitoring flash memory erase progress using erase credits202111,037,630NAND temperature data management202110,977,186Last written page searching202110,936,416Redundant array of independent NAND for a three-dimensional memory array202110,936,392Read window size202110,936,210Apparatuses and methods to control memory operations on buffers202110,929,056Interruption of program operations at a memory sub-system202110,930,352Temperature sensitive NAND programming202110,877,679Partially written block treatment202010,770,156Memory devices and methods for read disturb mitigation involving word line scans to detect localized read disturb effects and to determine error count in tracked sub sets of memory addresses202010,755,793SLC page read202010,679,704NAND temperature data management202010,510,422Memory devices with read level calibration201910,446,237Temperature sensitive NAND programming201910,423,350Partially written block treatment201910,372,353Apparatuses and methods to control memory operations on buffers201910,359,963Partially written block treatment201910,354,732NAND temperature data management201910,340,016Methods of error-based read disturb mitigation and memory devices utilizing the same201910,318,378Redundant array of independent NAND for a three-dimensional memory array201910,199,111Memory devices with read level calibration20199,620,229'Three dimensional memory control circuitry'20179,471,425'Data conditioning to improve flash memory reliability'20169,202,536'Three dimensional memory control circuitry'20159,196,370'Reducing noise in semiconductor devices'20159,158,612'Refresh of non-volatile memory cells based on fatigue conditions'20159,093,162'Sensing memory cells'20158,995,182'Coarse and fine programming in a solid state memory'20158,976,582'Analog sensing of memory cells in a solid-state memory device'20158,953,374'Programming based on controller performance requirements'20158,787,103'Analog-to-digital and digital-to-analog conversion window adjustment based on reference cells in a memory device'20148,773,912'Soft landing for desired program threshold voltage'20148,762,629'Data conditioning to improve flash memory reliability'20148,737,127'Memory controllers to output data signals of a number of bits and to receive data signals of a different number of bits'20148,719,665'Programming error correction code into a solid state memory device with varying bits per cell'20148,713,246'Memory device program window adjustment'20148,707,112'Refresh of non-volatile memory cells based on fatigue conditions'20148,693,246'Memory controller self-calibration for removing systemic influence'20148,687,430'Analog sensing of memory cells with a source follower driver in a semiconductor memory device'20148,644,070'Cell deterioration warning apparatus and method'20148,611,149'Programming based on controller performance requirements'20138,578,244'Programming error correction code into a solid state memory device with varying bits per cell'20138,565,024'Sensing memory cells'20138,553,458'Methods for segmented programming and memory devices'20138,526,243'Configurable digital and analog input/output interface in a memory device'20138,488,385'Reducing noise in semiconductor devices'20138,467,250'Analog sensing of memory cells with a source follower driver in a semiconductor memory device'20138,441,858'Apparatus having a string of memory cells'20138,422,310'Analog sensing of memory cells with a source follower driver in a semiconductor memory device'20138,400,826'Coarse and fine programming in a solid state memory'20138,385,121'Memory adapted to program a number of bits to a memory cell and read a different number of bits from the memory cell'20138,379,446'Memory controller self-calibration for removing systemic influence'20138,345,482'Methods for segmented programming and memory devices'20138,307,152'Memory device program window adjustment'20128,289,779'Memory cell sensing device equipped with a ramp voltage generator using a digital-to-analog converter (DAC) and counters, and sensing methods thereof'20128,289,776'Expanded programming window for non-volatile multilevel memory cells'20128,291,271'Programming error correction code into a solid state memory device with varying bits per cell'20128,281,061'Data conditioning to improve flash memory reliability'20128,274,833'Mitigation of data corruption from back pattern and program disturb in a non-volatile memory device'20128,259,491'Coarse and fine programming in a solid state memory'20128,254,180'Methods of operating memories including characterizing memory cell signal lines'20128,254,182'Analog sensing of memory cells with a source follower driver in a semiconductor memory device'20128,243,513'Non-volatile multilevel memory cells with data read of reference cells'20128,223,551'Soft landing for desired program threshold voltage'20128,174,919'Apparatus and method for increasing data line noise tolerance'20128,169,832'Methods of erase verification for a flash memory device'20128,117,375'Memory device program window adjustment'20128,111,550'M+N bit programming and M+L bit read for M bit memory cells'20128,107,296'Mitigation of data corruption from back pattern and program disturb in a non-volatile memory device'20128,103,940'Programming error correction code into a solid state memory device with varying bits per cell'20128,102,706'Programming a memory with varying bits per cell'20128,085,596'Reducing noise in semiconductor devices'20118,060,798'Refresh of non-volatile memory cells based on fatigue conditions'20118,023,334'Program window adjust for memory cell signal line delay'20118,023,332'Cell deterioration warning apparatus and method'20118,023,324'Memory controller self-calibration for removing systemic influence'20118,006,166'Programming error correction code into a solid state memory device with varying bits per cell'20118,004,887'Configurable digital and analog input/output interface in a memory device'20117,995,412'Analog-to-digital and digital-to-analog conversion window adjustment based on reference cells in a memory device'20117,957,196'Method of programming memory cells of series strings of memory cells'20117,948,802'Sensing memory cells'20117,936,599'Coarse and fine programming in a solid state memory'20117,916,536'Programming based on controller performance requirements'20117,898,885'Analog sensing of memory cells in a solid state memory device'20117,872,912'M+N bit programming and M+L bit read for M bit memory cells'20117,872,911'Non-volatile multilevel memory cells with data read of reference cells'20117,864,584'Expanded programming window for non-volatile multilevel memory cells'20117,843,725'M+L bit read column architecture for M bit memory cells'20107,835,190'Methods of erase verification for a flash memory device'20107,830,718'Mitigation of data corruption from back pattern and program disturb in a non-volatile memory device'20107,826,290'Apparatus and method for increasing data line noise tolerance'20107,817,467'Memory controller self-calibration for removing systemic influence'20107,751,253'Analog sensing of memory cells with a source follower driver in a semiconductor memory device'20107,751,245'Programming sequence in NAND memory'20107,729,167'Programming a memory with varying bits per cell'20107,663,926'Cell deterioration warning apparatus and method'20107,639,532'Non-equal threshold voltage ranges in MLC NAND'20097,633,798'M+N bit programming and M+L bit read for M bit memory cells'20097,577,036'Non-volatile multilevel memory cells with data read of reference cells'20097,460,398'Programming a memory with varying bits per cell'20086,677,793'Automatic delay matching circuit for data serializer'20046,081,603'Method and apparatus for automatic gain control using a linear limiter circuit with voltage controlled resistors as a variable element'20006,035,049'AC coupling and signal amplification using switched capacitors'20005,859,803'Non-volatile circuit that disables failed devices'19995,386,160'Trim correction circuit with temperature coefficient compensation'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995Based in San Jose, CA, US· patent location history
1999–2021Based in Newark, CA, US· patent location history
2008–2021Patents assigned to MICRON TECHNOLOGY INC (97)· patent assignee history
2009–2017Based in Fremont, CA, US· patent location history
2011–2015Patents assigned to SARIN VISHAL (35)· patent assignee history
2011–2015Patents assigned to ROOHPARVAR FRANKIE F (31)· patent assignee history
2011–2015Patents assigned to HOEI JUNG-SHENG (25)· patent assignee history
2012–2014Patents assigned to PABUSTAN JONATHAN (8)· patent assignee history
2013–2015Based in Freemont, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 97 | 2008–2021 |
| SARIN VISHAL | 35 | 2011–2015 |
| ROOHPARVAR FRANKIE F | 31 | 2011–2015 |
| HOEI JUNG-SHENGself | 25 | 2011–2015 |
| PABUSTAN JONATHAN | 8 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Newark, California, US | 77 | 1999–2021 |
| Fremont, California, US | 26 | 2009–2017 |
| Freemont, California, US | 3 | 2013–2015 |
| San Jose, California, US | 1 | 1995 |