Inventor

Joel A. Drewes

Inventor

Boise, ID, US

Overview

2002–2013

Patent span

Electricity

Primary field (CPC H)

Patents· 61 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Nprimary

H10NElectric solid-state devices not otherwise provided for20%

H10BElectronic memory devices19%

G11CStatic stores16%

B82YSpecific uses or applications of nanostructures11%

H01FMagnets8%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h106%

H10DInorganic electric semiconductor devices5%

C23CCoating metallic material4%

C12QMeasuring or testing processes involving enzymes, nucleic acids or microorganisms1%

PatentTitleYear

8,565,016'System having improved surface planarity for bit material deposition'2013 8,368,133'Memory constructions comprising magnetic materials'2013 7,947,597'Methods of titanium deposition'2011 7,943,507'Atomic layer deposition systems and methods including silicon-containing tantalum precursor compounds'2011 7,902,580'Assemblies comprising magnetic elements and magnetic barrier or shielding'2011 7,884,405'Method for production of MRAM elements'2011 7,855,085'System and method for reducing shorting in memory cells'2010 7,700,480'Methods of titanium deposition'2010 7,662,649'Methods for assessing alignments of substrates within deposition apparatuses; and methods for assessing thicknesses of deposited layers within deposition apparatuses'2010 7,622,388'Methods of forming titanium-containing materials'2009 7,605,417'Assemblies comprising magnetic elements and magnetic barrier or shielding at least partially around the magnetic elements'2009 7,585,371'Substrate susceptors for receiving semiconductor substrates to be deposited upon'2009 7,538,392'Pseudo SOI substrate and associated semiconductor devices'2009 7,521,356'Atomic layer deposition systems and methods including silicon-containing tantalum precursor compounds'2009 7,517,704'MRAM layer having domain wall traps'2009 7,470,552'Method for production of MRAM elements'2008 7,427,514'Passivated magneto-resistive bit structure and passivation method therefor'2008 7,402,879'Layered magnetic structures having improved surface planarity for bit material deposition'2008 7,402,833'Multilayer dielectric tunnel barrier used in magnetic tunnel junction devices, and its method of fabrication'2008 7,375,388'Device having improved surface planarity prior to MRAM bit material deposition'2008 7,371,587'Method for reducing diffusion through ferromagnetic materials'2008 7,361,596'Semiconductor processing methods'2008 7,358,553'System and method for reducing shorting in memory cells'2008 7,268,023'Method of forming a pseudo SOI substrate and semiconductor devices'2007 7,267,999'MRAM layer having domain wall traps'2007 7,264,844'Forming oxide buffer layer for improved magnetic tunnel junctions'2007 7,235,409'Methods of forming semiconductor constructions'2007 7,214,547'Methods of forming semiconductor constructions'2007 7,208,323'Method for forming magneto-resistive memory cells with shape anisotropy'2007 7,189,583'Method for production of MRAM elements'2007 7,170,123'Antiferromagnetically stabilized pseudo spin valve for memory applications'2007 7,161,219'MRAM devices with fine tuned offset'2007 7,161,201'Antiferromagnetically stabilized pseudo spin valve for memory applications'2007 7,153,651'Flow-through optical assay devices providing laminar flow of fluid samples, and methods of construction thereof'2006 7,112,454'System and method for reducing shorting in memory cells'2006 7,063,985'Method for fabricating sensor devices having improved switching properties'2006 7,034,374'MRAM layer having domain wall traps'2006 7,001,779'Methods of forming semiconductor constructions'2006 6,933,112'Device for mass transport assisted optical assays'2005 6,927,466'Magnetoresistive memory or sensor devices having improved switching properties and method of fabrication'2005 6,906,950'Magneto-resistive memory cell with shape anistropy and memory device thereof'2005 6,903,399'Antiferromagnetically stabilized pseudo spin valve for memory applications'2005 6,902,940'Method for manufacture of MRAM memory elements'2005 6,900,489'Reducing the effects of nÃ©el coupling in MRAM structures'2005 6,900,455'Multilayer dielectric tunnel barrier used in magnetic tunnel junction devices, and its method of fabrication'2005 6,885,073'Method and apparatus providing MRAM devices with fine tuned offset'2005 6,881,993'Device having reduced diffusion through ferromagnetic materials'2005 6,870,714'Oxide buffer layer for improved magnetic tunnel junctions'2005 6,852,550'MRAM sense layer area control'2005 6,849,464'Method of fabricating a multilayer dielectric tunnel barrier structure'2005 6,806,546'Passivated magneto-resistive bit structure'2004 6,781,173'MRAM sense layer area control'2004 6,743,641'Method of improving surface planarity prior to MRAM bit material deposition'2004 6,707,084'Antiferromagnetically stabilized pseudo spin valve for memory applications'2004 6,689,622'Magnetoresistive memory or sensor devices having improved switching properties and method of fabrication'2004 6,683,806'Methods of operating MRAM devices'2004 6,677,631'MRAM memory elements and method for manufacture of MRAM memory elements'2004 6,656,371'Methods of forming magnetoresisitive devices'2003 6,627,932'Magnetoresistive memory device'2003 6,623,987'Passivated magneto-resistive bit structure and passivation method therefor'2003 6,392,922'Passivated magneto-resistive bit structure and passivation method therefor'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2002–2013Patents assigned to MICRON TECHNOLOGY INC (58)· patent assignee history

2002–2008Based in Minnetonka, MN, US· patent location history

2003–2013Based in Boise, ID, US· patent location history

2005Patents assigned to THERMO BIOSTAR INC (1)· patent assignee history

2005–2006Based in Woodbridge, VA, US· patent location history

2006Patents assigned to INVERNESS MEDICAL BIOSTAR INC (1)· patent assignee history

2009–2013Based in Longmont, CO, US· patent location history

2011Patents assigned to ROUND ROCK RES LLC (1)· patent assignee history

2013Patents assigned to DREWES JOEL A (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MICRON TECHNOLOGY INC	58	2002–2013
DREWES JOEL Aself	2	2013
INVERNESS MEDICAL BIOSTAR INC	1	2006
ROUND ROCK RES LLC	1	2011
THERMO BIOSTAR INC	1	2005

Locations

Location	Patents	Span
Boise, ID, US	49	2003–2013
Longmont, CO, US	6	2009–2013
Minnetonka, Minnesota, US	4	2002–2008
Woodbridge, Virginia, US	2	2005–2006