Inventor
GUILLAUME BOUCHE
Inventor
US
Overview
Patents· 23 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices30%
H10DInorganic electric semiconductor devices28%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1024%
B82YSpecific uses or applications of nanostructures10%
H10BElectronic memory devices4%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h104%
PatentTitleYear
12,512,407Stitching to enable dense interconnect arrangements202512,506,076Power rail between fins of a transistor structure202512,439,659Gate-all-around integrated circuit structures having germanium-diffused nanoribbon channel structures202512,376,353Source/drain regions in integrated circuit structures202512,328,936Gate spacing in integrated circuit structures202512,315,805Self-aligned lateral contacts202512,237,388Transistor arrangements with stacked trench contacts and gate straps202512,211,786Stacked vias with bottom portions formed using selective growth202512,211,898Device contact sizing in integrated circuit structures202512,148,751Use of a placeholder for backside contact formation for transistor arrangements202412,142,516Self aligned buried power rail202412,094,822Buried power rails with self-aligned vias to trench contacts202411,984,487Non-planar transistor arrangements with asymmetric gate enclosures202411,973,121Device contacts in integrated circuit structures202411,916,010Back end of line integration for self-aligned vias202411,916,106Source/drain regions in integrated circuit structures202411,749,715Isolation regions in integrated circuit structures202311,482,524Gate spacing in integrated circuit structures202211,450,736Source/drain regions in integrated circuit structures202211,430,866Device contact sizing in integrated circuit structures202211,342,409Isolation regions in integrated circuit structures202211,309,210Self aligned buried power rail202211,264,463Multiple fin finFET with low-resistance gate structure2022Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2022–2025Patents assigned to INTEL CORP (19)· patent assignee history
2022–2024Patents assigned to GLOBALFOUNDRIES US INC (2)· patent assignee history
2022Patents assigned to GLOBALFOUNDRIES INC (1)· patent assignee history
2022–2025Based in US· patent location history
2022–2024Based in BE· patent location history
2025Patents assigned to Intel NDTM US LLC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 19 | 2022–2025 |
| GLOBALFOUNDRIES US INC | 2 | 2022–2024 |
| GLOBALFOUNDRIES INC | 1 | 2022 |
| Intel NDTM US LLC | 1 | 2025 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 21 | 2022–2025 |
| BE | 2 | 2022–2024 |