Inventor
Mattheus Cornelis Antonius Adrianus Heddes
Inventor
Raleigh, NC, US
Overview
Patents· 18 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing46%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use17%
G11CStatic stores11%
H03MCoding11%
G06NComputing arrangements based on specific computational models9%
H04LTransmission of digital information, e.g. telegraphic communication3%
H04QSelecting3%
PatentTitleYear
11,076,210Distributed processing architecture202110,936,943Providing flexible matrix processors for performing neural network convolution in matrix-processor-based devices202110,838,862Memory controllers employing memory capacity compression, and related processor-based systems and methods202010,747,501Providing efficient floating-point operations using matrix processors in processor-based systems202010,725,740Providing efficient multiplication of sparse matrices in matrix-processor-based devices202010,503,661Providing memory bandwidth compression using compressed memory controllers (CMCs) in a central processing unit (CPU)-based system201910,467,092Providing space-efficient storage for dynamic random access memory (DRAM) cache tags201910,236,917Providing memory bandwidth compression in chipkill-correct memory architectures201910,191,850Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system201910,176,090Providing memory bandwidth compression using adaptive compression in central processing unit (CPU)-based systems201910,176,096Providing scalable dynamic random access memory (DRAM) cache management using DRAM cache indicator caches201910,152,261Providing memory bandwidth compression using compression indicator (CI) hint directories in a central processing unit (CPU)-based system201810,146,693Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system201810,067,706Providing memory bandwidth compression using compression indicator (CI) hint directories in a central processing unit (CPU)-based system201810,055,158Providing flexible management of heterogeneous memory systems using spatial quality of service (QoS) tagging in processor-based systems201810,042,771Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system20189,740,621'Memory controllers employing memory capacity and/or bandwidth compression with next read address prefetching, and related processor-based systems and methods'20175,450,351'Content addressable memory implementation with random access memory'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995Patents assigned to IBM (1)· patent assignee history
1995Based in Kilchberg, CH· patent location history
2017–2021Patents assigned to QUALCOMM INC (15)· patent assignee history
2017–2020Based in Raleigh, NC, US· patent location history
2020–2021Based in Woodinville, WA, US· patent location history
2021Patents assigned to MICROSOFT TECHNOLOGY LICENSING LLC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| QUALCOMM INC | 15 | 2017–2021 |
| IBM | 1 | 1995 |
| MICROSOFT TECHNOLOGY LICENSING LLC | 1 | 2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| Raleigh, NC, US | 13 | 2017–2020 |
| Woodinville, Washington, US | 4 | 2020–2021 |
| Kilchberg, CH | 1 | 1995 |