Inventor

Doron Orenstein

Inventor

Haifa, IL

Overview

1995–2021

Patent span

Physics

Primary field (CPC G)

Patents· 30 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing80%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use11%

G06TImage data processing or generation, in general6%

G11CStatic stores3%

PatentTitleYear

11,048,507Compressed instruction format2021 10,831,477In-lane vector shuffle instructions2020 10,514,918In-lane vector shuffle instructions2019 10,514,917In-lane vector shuffle instructions2019 10,514,916In-lane vector shuffle instructions2019 10,509,652In-lane vector shuffle instructions2019 10,095,515Compressed instruction format2018 9,672,034'Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of per-lane control bits'2017 9,569,208'Compressed instruction format'2017 9,235,415'Permute operations with flexible zero control'2016 9,086,872'Unpacking packed data in multiple lanes'2015 9,081,562'Unpacking packed data in multiple lanes'2015 8,914,613'Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of per-lane control bits'2014 8,756,403'Compressed instruction format'2014 8,281,109'Compressed instruction format'2012 8,078,836'Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a common set of per-lane control bits'2011 8,078,831'Method and apparatus for affinity-guided speculative helper threads in chip multiprocessors'2011 7,849,465'Programmable event driven yield mechanism which may activate service threads'2010 7,844,801'Method and apparatus for affinity-guided speculative helper threads in chip multiprocessors'2010 7,721,129'Method and apparatus for reducing clock frequency during low workload periods'2010 7,437,581'Method and apparatus for varying energy per instruction according to the amount of available parallelism'2008 7,051,227'Method and apparatus for reducing clock frequency during low workload periods'2006 6,944,720'Memory system for multiple data types'2005 6,886,105'Method and apparatus for resuming memory operations from a low latency wake-up low power state'2005 6,724,391'Mechanism for implementing Z-compression transparently'2004 6,580,427'Z-compression mechanism'2003 6,557,083'Memory system for multiple data types'2003 5,835,748'Method for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file'1998 5,787,026'Method and apparatus for providing memory access in a processor pipeline'1998 5,450,605'Boundary markers for indicating the boundary of a variable length instruction to facilitate parallel processing of sequential instructions'1995

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1995–2021Patents assigned to INTEL CORP (30)· patent assignee history

1995–2021Based in Haifa, IL· patent location history

1998Based in Halfa, IL· patent location history

2011–2017Patents assigned to ORENSTEIN DORON (6)· patent assignee history

2011–2017Patents assigned to VALENTINE ROBERT (4)· patent assignee history

2011–2014Patents assigned to EITAN BENNY (2)· patent assignee history

2011–2014Patents assigned to SPERBER ZEEV (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	30	1995–2021
ORENSTEIN DORONself	6	2011–2017
VALENTINE ROBERT	4	2011–2017
EITAN BENNY	2	2011–2014
SPERBER ZEEV	2	2011–2014

Locations

Location	Patents	Span
Haifa, IL	29	1995–2021
Halfa, IL	1	1998