Inventor
Suryanarayan G. Hegde
Inventor
Hollowville, NY, US
Overview
Patents· 20 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices34%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1026%
G11BInformation storage based on relative movement between record carrier and transducer11%
H10BElectronic memory devices9%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%
G01BMeasuring length, thickness or similar linear dimensions3%
G01NInvestigating or analysing materials by determining their chemical or physical properties3%
G01RMeasuring electric variables3%
G06FElectric digital data processing3%
H04LTransmission of digital information, e.g. telegraphic communication3%
PatentTitleYear
11,050,644Dynamic device anchoring to SD-WAN cluster20217,453,123'Self-aligned planar double-gate transistor structure'20087,205,185'Self-aligned planar double-gate process by self-aligned oxidation'20076,878,978'CMOS performance enhancement using localized voids and extended defects'20056,858,488'CMOS performance enhancement using localized voids and extended defects'20056,833,569'Self-aligned planar double-gate process by amorphization'20046,803,270'CMOS performance enhancement using localized voids and extended defects'20046,727,142'Orientation independent oxidation of nitrided silicon'20046,569,781'Method of forming an ultra-thin oxide layer on a silicon substrate by implantation of nitrogen through a sacrificial layer and subsequent annealing prior to oxide formation'20036,514,843'Method of enhanced oxidation of MOS transistor gate corners'20036,387,782'Process of forming an ultra-shallow junction dopant layer having a peak concentration within a dielectric layer'20026,348,388'Process for fabricating a uniform gate oxide of a vertical transistor'20026,329,704'Ultra-shallow junction dopant layer having a peak concentration within a dielectric layer'20016,297,086'Application of excimer laser anneal to DRAM processing'20016,150,670'Process for fabricating a uniform gate oxide of a vertical transistor'20005,977,787'Large area multiple-chip probe assembly and method of making the same'19995,875,171'Interlocking disk stack that prevents disk slip in a storage disk'19995,392,177'Sealed DASD having humidity control and method of making same'19955,115,664'Tunable feedback transducer for transient friction measurement'19924,931,887'Capacitive measurement and control of the fly height of a recording slider'1990Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1990–2008Patents assigned to IBM (19)· patent assignee history
1990–2008Based in Hollowville, NY, US· patent location history
2000–2002Patents assigned to INFINEON TECHNOLOGIES CORP (4)· patent assignee history
2000–2005Based in New York, NY, US· patent location history
2021Patents assigned to HEWLETT PACKARD ENTPR DEV LP (1)· patent assignee history
2021Based in Bangalore, IN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 19 | 1990–2008 |
| INFINEON TECHNOLOGIES CORP | 4 | 2000–2002 |
| HEWLETT PACKARD ENTPR DEV LP | 1 | 2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hollowville, New York, US | 12 | 1990–2008 |
| New York, New York, US | 7 | 2000–2005 |
| Bangalore, IN | 1 | 2021 |