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Inventor

Steve Durrill

Inventor
Campbell, CA, US

Overview

4→
Patents
2007–2014
Patent span
Physics
Primary field (CPC G)

Patents· 4 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing100%
PatentTitleYear
8,898,039'Physical topology-driven logical design flow'20148,732,651'Logical design flow with structural compatability verification'20148,271,933'Pin unspecific device planning for printed circuit board layout'20127,168,041'Method and apparatus for table and HDL based design entry'2007

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2007–2014Patents assigned to CADENCE DESIGN SYSTEMS INC (4)· patent assignee history
2007Based in San Jose, CA, US· patent location history
2012–2014Based in Campbell, CA, US· patent location history
2014Patents assigned to DURRILL STEVE (2)· patent assignee history
2014Patents assigned to GUPTA NIKHIL (2)· patent assignee history
2014Patents assigned to KHANNA VIKRANT (2)· patent assignee history
2014Patents assigned to KUKAL TARANJIT SINGH (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
CADENCE DESIGN SYSTEMS INC42007–2014
DURRILL STEVEself22014
GUPTA NIKHIL22014
KHANNA VIKRANT22014
KUKAL TARANJIT SINGH22014
Locations
LocationPatentsSpan
Campbell, California, US32012–2014
San Jose, California, US12007