Inventor
Natarajan Viswanathan
Inventor
Austin, TX, US
Overview
Patents· 34 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing85%
H03KPulse technique13%
Y02PClimate change mitigation technologies in the production or processing of goods3%
PatentTitleYear
10,963,617Modifying route topology to fix clock tree violations202110,685,160Large cluster persistence during placement optimization of integrated circuit designs202010,402,522Region aware clustering201910,318,693Balanced scaled-load clustering201910,289,797Local cluster refinement201910,140,409Large cluster persistence during placement optimization of integrated circuit designs20189,870,097'Noise cancellation technique for capacitive touchscreen controller using differential sensing'20189,524,363'Element placement in circuit design based on preferred location'20169,495,501'Large cluster persistence during placement optimization of integrated circuit designs'20169,442,610'Noise cancellation technique for capacitive touchscreen controller using differential sensing'20169,391,607'Use of random sampling technique to reduce finger-coupled noise'20169,251,306'Alignment net insertion for straightening the datapath in a force-directed placer'20169,098,669'Boundary latch and logic placement to satisfy timing constraints'20158,954,912'Structured placement of latches/flip-flops to minimize clock power in high-performance designs'20158,830,207'Method and apparatus for improving dynamic range of a touchscreen controller'20148,793,636'Placement of structured nets'20148,782,584'Post-placement cell shifting'20148,769,457'Separate refinement of local wirelength and local module density in intermediate placement of an integrated circuit design'20148,683,411'Electronic design automation object placement with partially region-constrained objects'20148,677,299'Latch clustering with proximity to local clock buffers'20148,667,441'Clock optimization with local clock buffer control optimization'20148,595,675'Local objective optimization in global placement of an integrated circuit design'20138,589,848'Datapath placement using tiered assignment'20138,493,356'Noise cancellation technique for capacitive touchscreen controller using differential sensing'20138,495,548'Multi-patterning lithography aware cell placement in integrated circuit design'20138,495,534'Post-placement cell shifting'20138,458,634'Latch clustering with proximity to local clock buffers'20138,453,093'Alignment net insertion for straightening the datapath in a force-directed placer'20138,418,108'Accuracy pin-slew mode for gate delay calculation'20138,347,257'Detailed routability by cell placement'20138,347,249'Incremental timing optimization and placement'20137,934,188'Legalization of VLSI circuit placement with blockages using hierarchical row slicing'20117,882,475'Method to reduce the wirelength of analytical placement techniques by modulation of spreading forces vectors'20117,266,796'Fastplace method for integrated circuit design'2007Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2007Based in Ames, IA, US· patent location history
2011–2020Patents assigned to IBM (22)· patent assignee history
2011–2021Based in Austin, TX, US· patent location history
2013–2016Patents assigned to VISWANATHAN NATARAJAN (16)· patent assignee history
2013–2016Patents assigned to ALPERT CHARLES J (11)· patent assignee history
2013–2016Patents assigned to NAM GI-JOON (11)· patent assignee history
2013–2014Patents assigned to LI ZHUO (8)· patent assignee history
2013–2018Based in Sunnyvale, CA, US· patent location history
2014–2016Based in Saratoga, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 22 | 2011–2020 |
| VISWANATHAN NATARAJANself | 16 | 2013–2016 |
| ALPERT CHARLES J | 11 | 2013–2016 |
| NAM GI-JOON | 11 | 2013–2016 |
| LI ZHUO | 8 | 2013–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 28 | 2011–2021 |
| Sunnyvale, California, US | 3 | 2013–2018 |
| Saratoga, California, US | 2 | 2014–2016 |
| Ames, IA, US | 1 | 2007 |