Inventor

Tolga Ozguner

Inventor

Rochester, MN, US

Overview

34→

Patents

2005–2020

Patent span

Physics

Primary field (CPC G)

Patents· 34 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing28%

G06TImage data processing or generation, in general12%

H04LTransmission of digital information, e.g. telegraphic communication12%

G02BOptical elements, systems or apparatus11%

G09GArrangements or circuits for control of indicating devices using static means to present variable information9%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use9%

G11CStatic stores7%

G03HHolographic processes or apparatus4%

H04NPictorial communication, e.g. television4%

A61MDevices for introducing media into, or onto, the body1%

PatentTitleYear

10,672,368No miss cache structure for real-time image transformations with multiple LSR processing engines2020 10,514,753Selectively applying reprojection processing to multi-layer scenes for optimizing late stage reprojection power2019 10,410,349Selective application of reprojection processing on layer sub-regions for optimizing late stage reprojection power2019 10,403,029Methods and systems for multistage post-rendering image transformation2019 10,360,832Post-rendering image transformation using parallel image transformation pipelines2019 10,338,816Reducing negative effects of insufficient data throughput for real-time processing2019 10,255,891No miss cache structure for real-time image transformations with multiple LSR processing engines2019 10,242,654No miss cache structure for real-time image transformations2019 10,241,470No miss cache structure for real-time image transformations with data compression2019 10,095,408Reducing negative effects of insufficient data throughput for real-time processing2018 9,978,118No miss cache structure for real-time image transformations with data compression2018 9,747,225'Interrupt controller'2017 8,219,745'Memory controller to utilize DRAM write buffers'2012 8,213,428'Methods and apparatus for indexing memory of a network processor'2012 8,170,024'Implementing pointer and stake model for frame alteration code in a network processor'2012 7,925,823'Reuse of functional data buffers for pattern buffers in XDR DRAM'2011 7,761,682'Memory controller operating in a system with a variable system clock'2010 7,757,006'Implementing conditional packet alterations based on transmit port'2010 7,757,040'Memory command and address conversion between an XDR interface and a double data rate interface'2010 7,752,379'Managing write-to-read turnarounds in an early read after write memory system'2010 7,669,028'Optimizing data bandwidth across a variable asynchronous clock domain'2010 7,487,318'Managing write-to-read turnarounds in an early read after write memory system'2009 7,475,161'Implementing conditional packet alterations based on transmit port'2009 7,467,277'Memory controller operating in a system with a variable system clock'2008 7,380,052'Reuse of functional data buffers for pattern buffers in XDR DRAM'2008 7,330,478'Method, apparatus, and computer program product for implementing pointer and stake model for frame alteration code in a network processor'2008 7,321,950'Method and apparatus for managing write-to-read turnarounds in an early read after write memory system'2008 7,239,635'Method and apparatus for implementing alterations on multiple concurrent frames'2007 7,225,097'Methods and apparatus for memory calibration'2007 7,224,701'Method and apparatus for implementing frame header alterations using byte-wise arithmetic logic units'2007 7,218,647'Method and apparatus for implementing frame header alterations'2007 6,996,650'Method and apparatus for implementing multiple configurable sub-busses of a point-to-point bus'2006 6,910,092'Chip to chip interface for interconnecting chips'2005 6,880,026'Method and apparatus for implementing chip-to-chip interconnect bus initialization'2005

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2005–2012Patents assigned to IBM (22)· patent assignee history

2005–2012Based in Rochester, MN, US· patent location history

2012Patents assigned to OZGUNER TOLGA (3)· patent assignee history

2012Patents assigned to BELLOWS MARK DAVID (1)· patent assignee history

2012Patents assigned to FAGERNESS GERALD G (1)· patent assignee history

2017–2020Patents assigned to MICROSOFT TECHNOLOGY LICENSING LLC (12)· patent assignee history

2017–2020Based in Redmond, WA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	22	2005–2012
MICROSOFT TECHNOLOGY LICENSING LLC	12	2017–2020
OZGUNER TOLGAself	3	2012
BELLOWS MARK DAVID	1	2012
FAGERNESS GERALD G	1	2012

Locations

Location	Patents	Span
Rochester, Minnesota, US	22	2005–2012
Redmond, Washington, US	12	2017–2020