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Inventor

Andrew Ferko

Inventor
Waterbury, VT, US

Overview

4→
Patents
2004–2012
Patent span
Physics
Primary field (CPC G)

Patents· 4 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G01Rprimary
G01RMeasuring electric variables80%
G06FElectric digital data processing20%
PatentTitleYear
8,209,141'System and method for automatically generating test patterns for at-speed structural test of an integrated circuit device using an incremental approach to reduce test pattern count'20127,900,112'System and method for digital logic testing'20117,103,816'Method and system for reducing test data volume in the testing of logic products'20066,782,501'System for reducing test data volume in the testing of logic products'2004

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2004–2006Patents assigned to CADENCE DESIGN SYSTEMS INC (2)· patent assignee history
2004–2012Based in Waterbury, VT, US· patent location history
2011–2012Patents assigned to IBM (2)· patent assignee history
2012Patents assigned to BASSETT ROBERT W (1)· patent assignee history
2012Patents assigned to FERKO ANDREW (1)· patent assignee history
2012Patents assigned to IYENGAR VIKRAM (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
CADENCE DESIGN SYSTEMS INC22004–2006
IBM22011–2012
BASSETT ROBERT W12012
FERKO ANDREWself12012
IYENGAR VIKRAM12012
Locations
LocationPatentsSpan
Waterbury, VT, US42004–2012