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Inventor

Yinan Shen

Inventor
Sunnyvale, CA, US

Overview

6→
Patents
2004–2019
Patent span
Physics
Primary field (CPC G)

Patents· 6 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing100%
PatentTitleYear
10,262,096Component placement with repacking for programmable logic devices20198,112,731'Congestion-driven placement systems and methods for programmable logic devices'20128,086,986'Clock boosting systems and methods'20117,509,598'Clock boosting systems and methods'20097,000,210'Adaptive adjustment of constraints during PLD placement processing'20066,813,754'Placement processing for programmable logic devices'2004

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2004–2019Patents assigned to LATTICE SEMICONDUCTOR CORP (6)· patent assignee history
2004–2012Based in Sunnyvale, CA, US· patent location history
2006Based in Santa Clara, CA, US· patent location history
2011–2012Patents assigned to SHEN YINAN (2)· patent assignee history
2011Patents assigned to XU SONG (1)· patent assignee history
2012Patents assigned to CHEN CHIH-CHUNG (1)· patent assignee history
2012Patents assigned to WANG BO (1)· patent assignee history
2019Based in San Jose, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
LATTICE SEMICONDUCTOR CORP62004–2019
SHEN YINANself22011–2012
CHEN CHIH-CHUNG12012
WANG BO12012
XU SONG12011
Locations
LocationPatentsSpan
Sunnyvale, California, US42004–2012
San Jose, California, US12019
Santa Clara, California, US12006