Inventor

Michael C. Smayling

Inventor

Fremont, CA, US

Overview

1981–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 227 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices23%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1018%

G06FElectric digital data processing17%

H01LSemiconductor devices6%

H10BElectronic memory devices6%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices4%

G11CStatic stores3%

H01JElectric discharge tubes or discharge lamps2%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%

PatentTitleYear

11,037,756Precision substrate material multi-processing using miniature-column charged particle beam arrays2021 10,978,303Secure permanent integrated circuit personalization2021 10,734,192Precision substrate material multi-processing using miniature-column charged particle beam arrays2020 10,734,383Methods, structures, and designs for self-aligning local interconnects used in integrated circuits2020 10,659,229Secure permanent integrated circuit personalization2020 10,658,153Precision substrate material multi-processing using miniature-column charged particle beam arrays2020 10,607,845Patterned atomic layer etching and deposition using miniature-column charged particle beam arrays2020 10,461,081Super-self-aligned contacts and method for making the same2019 10,341,108Secure permanent integrated circuit personalization2019 10,312,091Secure permanent integrated circuit personalization2019 10,217,763Semiconductor chip having region including gate electrode features of rectangular shape on gate horizontal grid and first-metal structures of rectangular shape on at least eight first-metal gridlines of first-metal vertical grid2019 10,186,523Semiconductor chip having region including gate electrode features formed in part from rectangular layout shapes on gate horizontal grid and first-metal structures formed in part from rectangular layout shapes on at least eight first-metal gridlines of first-metal vertical grid2019 10,141,334Semiconductor chip including region having rectangular-shaped gate structures and first-metal structures2018 10,141,335Semiconductor CIP including region having rectangular-shaped gate structures and first metal structures2018 10,074,640Integrated circuit cell library for multiple patterning2018 10,026,589Alignment and registration targets for charged particle beam substrate patterning and inspection2018 10,020,166Alignment and registration targets for charged particle beam substrate patterning and inspection2018 10,020,200Patterned atomic layer etching and deposition using miniature-column charged particle beam arrays2018 9,917,056'Coarse grid design methods and structures'2018 9,905,576'Semiconductor chip including region having rectangular-shaped gate structures and first metal structures'2018 9,881,817'Precision substrate material multi-processing using miniature-column charged particle beam arrays'2018 9,859,277'Methods, structures, and designs for self-aligning local interconnects used in integrated circuits'2018 9,822,443'Precision material modification using miniature-column charged particle beam arrays'2017 9,824,859'Precision material modification using miniature-column charged particle beam arrays'2017 9,818,747'Super-self-aligned contacts and method for making the same'2017 9,741,719'Methods, structures, and designs for self-aligning local interconnects used in integrated circuits'2017 9,704,845'Methods for linewidth modification and apparatus implementing the same'2017 9,673,114'Precision substrate material removal using miniature-column charged particle beam arrays'2017 9,633,987'Integrated circuit cell library for multiple patterning'2017 9,595,515'Semiconductor chip including integrated circuit defined within dynamic array section'2017 9,595,419'Alignment and registration targets for multiple-column charged particle beam lithography and inspection'2017 9,589,091'Scalable meta-data objects'2017 9,556,521'Precision deposition using miniature-column charged particle beam arrays'2017 9,478,395'Alignment and registration targets for multiple-column charged particle beam lithography and inspection'2016 9,466,464'Precision substrate material removal using miniature-column charged particle beam arrays'2016 9,453,281'Precision deposition using miniature-column charged particle beam arrays'2016 9,443,947'Semiconductor chip including region having integrated circuit transistor gate electrodes formed by various conductive structures of specified shape and position and method for manufacturing the same'2016 9,425,273'Semiconductor chip including integrated circuit including at least five gate level conductive structures having particular spatial and electrical relationship and method for manufacturing the same'2016 9,425,272'Semiconductor chip including integrated circuit including four transistors of first transistor type and four transistors of second transistor type with electrical connections between various transistors and methods for manufacturing the same'2016 9,336,344'Coarse grid design methods and structures'2016 9,281,371'Super-self-aligned contacts and method for making the same'2016 9,240,413'Methods, structures, and designs for self-aligning local interconnects used in integrated circuits'2016 9,159,627'Methods for linewidth modification and apparatus implementing the same'2015 9,122,832'Methods for controlling microloading variation in semiconductor wafer layout and fabrication'2015 9,035,359'Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods'2015 9,009,641'Circuits with linear finfet structures'2015 8,952,425'Integrated circuit including at least four linear-shaped conductive structures having extending portions of different length'2015 8,951,916'Super-self-aligned contacts and method for making the same'2015 8,946,781'Integrated circuit including gate electrode conductive structures with different extension distances beyond contact'2015 8,921,896'Integrated circuit including linear gate electrode structures having different extension distances beyond contact'2014 8,921,897'Integrated circuit with gate electrode conductive structures having offset ends'2014 8,863,063'Finfet transistor circuit'2014 8,839,175'Scalable meta-data objects'2014 8,823,062'Integrated circuit with offset line end spacings in linear gate electrode level'2014 8,759,882'Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos'2014 8,756,551'Methods for designing semiconductor device with dynamic array section'2014 8,680,626'Methods, structures, and designs for self-aligning local interconnects used in integrated circuits'2014 8,667,443'Integrated circuit cell library for multiple patterning'2014 8,658,542'Coarse grid design methods and structures'2014 8,541,879'Super-self-aligned contacts and method for making the same'2013 8,436,400'Semiconductor device with gate level including gate electrode conductors for transistors of first type and transistors of second type with some gate electrode conductors of different length'2013 8,356,268'Integrated circuit device including dynamic array section with gate level having linear conductive features on at least three side-by-side lines and uniform line end spacings'2013 8,286,107'Methods and systems for process compensation technique acceleration'2012 8,283,701'Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos'2012 8,264,009'Semiconductor device with linearly restricted gate level region including four transistors of first type and four transistors of second type with gate defining shapes of different length'2012 8,264,007'Semiconductor device including at least six transistor forming linear shapes including at least two different gate contact connection distances'2012 8,264,008'Semiconductor device including transistor forming linear shapes including gate portions and extending portions of different size'2012 8,258,552'Semiconductor device including at least six transistor forming linear shapes with at least two transistor forming linear shapes having offset ends'2012 8,258,551'Semiconductor device with gate level including transistors of first type and transistors of second type with corresponding gate contact placement restriction'2012 8,258,550'Semiconductor device including at least six transistor forming linear shapes including at least two transistor forming linear shapes having different extension distances beyond gate contact'2012 8,258,549'Semiconductor device including two transistors of first type having gates formed by conductors of different length respectively aligned with two transistors of second type having gates formed by conductors of different length'2012 8,258,548'Semiconductor device with gate level including four transistors of first type and four transistors of second type separated by non-diffusion region with restricted gate contact placement over separating non-diffusion region'2012 8,258,547'Semiconductor device with linearly restricted gate level region including two transistors of first type and two transistors of second type with offset gate contacts'2012 8,253,172'Semiconductor device with linearly restricted gate level region including four serially connected transistors of first type and four serially connected transistors of second type separated by non-diffusion region'2012 8,253,173'Semiconductor device with gate level including four transistors of first type and four transistors of second type separated by non-diffusion region and having at least two gate contacts positioned outside separating non-diffusion region'2012 8,245,180'Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same'2012 8,225,239'Methods for defining and utilizing sub-resolution features in linear topology'2012 8,217,428'Integrated circuit including gate electrode level region including at least three linear-shaped conductive structures of equal length having aligned ends and positioned at equal pitch and forming multiple gate electrodes of transistors of different type'2012 8,207,053'Electrodes of transistors with at least two linear-shaped conductive structures of different length'2012 8,198,656'Integrated circuit including gate electrode level region including at least four linear-shaped conductive structures of equal length having aligned ends and positioned at equal pitch and forming multiple gate electrodes of transistors of different type'2012 8,138,525'Integrated circuit including at least three linear-shaped conductive structures of different length each forming gate of different transistor'2012 8,134,183'Integrated circuit including linear-shaped conductive structures that have gate portions and extending portions of different size'2012 8,134,185'Integrated circuit having gate electrode level region including at least seven linear-shaped conductive structures at equal pitch including linear-shaped conductive structure forming transistors of two different types and at least three linear-shaped conductive structures having aligned ends'2012 8,134,184'Integrated circuit having gate electrode level region including at least four linear-shaped conductive structures with some outer-contacted linear-shaped conductive structures having larger outer extending portion than inner extending portion'2012 8,134,186'Integrated circuit including at least three linear-shaped conductive structures at equal pitch including linear-shaped conductive structure having non-gate portion length greater than gate portion length'2012 8,129,755'Integrated circuit with gate electrode level including at least four linear-shaped conductive structures of equal length and equal pitch with linear-shaped conductive structure forming one transistor'2012 8,129,754'Integrated circuit with gate electrode level including at least six linear-shaped conductive structures forming gate electrodes of transisters with at least one pair of linear-shaped conductive structures having offset ends'2012 8,129,756'Integrated circuit including at least six linear-shaped conductive structures forming gate electrodes of transistors with at least two different extension distances beyond conductive contacting structures'2012 8,129,752'Integrated circuit including a linear-shaped conductive structure forming one gate electrode and having length greater than or equal to one-half the length of linear-shaped conductive structure forming two gate electrodes'2012 8,129,819'Method of fabricating integrated circuit including at least six linear-shaped conductive structures at equal pitch including at least two linear-shaped conductive structures having non-gate portions of different length'2012 8,129,753'Integrated circuit including gate electrode level region including at least seven linear-shaped conductive structures of equal length positioned at equal pitch with at least two linear-shaped conductive structures each forming one transistor and having extending portion sized greater than gate portion'2012 8,129,757'Integrated circuit including at least six linear-shaped conductive structive structures at equal pitch including at least two linear-shaped conductive structures having non-gate portions of different length'2012 8,129,750'Integrated circuit including at least six linear-shaped conductive structures forming gate electrodes of transistors with at least two linear-shaped conductive structures of different length'2012 8,129,751'Integrated circuit including at least six linear-shaped conductive structures forming gate electrodes and including four conductive contacting structures having at least two different connection distances'2012 8,110,854'Integrated circuit device with linearly defined gate electrode level region and shared diffusion region of first type connected to shared diffusion region of second type through at least two interconnect levels'2012 8,101,975'Integrated circuit device with gate level region including non-gate linear conductive segment positioned within 965 nanometers of four transistors of first type and four transistors of second type'2012 8,089,102'Method for fabricating integrated circuit having three or more linear-shaped gate electrode level conductive segments of both equal length and equal pitch'2012 8,089,103'Integrated circuit device with gate level region including at least three linear-shaped conductive segments having offset line ends and forming three transistors of first type and one transistor of second type'2012 8,089,100'Integrated circuit with gate electrode level region including at least four linear-shaped conductive structures forming gate electrodes of transistors and including extending portions of at least two different sizes'2012 8,088,681'Method for fabricating integrated circuit including separated diffusion regions of different type each having four gate electrodes with each of two complementary gate electrode pairs formed from respective linear condcutive segment'2012 8,088,679'Method for fabricating integrated circuit with gate electrode level portion including at least two complementary transistor forming linear conductive segments and at least one non-gate linear conductive segment'2012 8,088,680'Method for fabricating integrated circuit having at least three linear-shaped gate electrode level conductive features of equal length positioned side-by-side at equal pitch'2012 8,089,098'Integrated circuit device and associated layout including linear gate electrodes of different transistor types next to linear-shaped non-gate conductive segment'2012 8,089,101'Integrated circuit device with gate electrode level region including two side-by-side ones of at least three linear-shaped conductive structures electrically connected to each other through non-gate level'2012 8,089,099'Integrated circuit device and associated layout including gate electrode level region of 965 NM radius with linear-shaped conductive segments on fixed pitch'2012 8,088,682'Method for fabricating integrated circuit with gate electrode level region including two side-by-side ones of at least three linear-shaped conductive structures electrically connected to each other through non-gate level'2012 8,089,104'Integrated circuit with gate electrode level region including multiple linear-shaped conductive structures forming gate electrodes of transistors and including uniformity extending portions of different size'2012 8,072,003'Integrated circuit device and associated layout including two pairs of co-aligned complementary gate electrodes with offset gate contact structures'2011 8,058,671'Semiconductor device having at least three linear-shaped electrode level conductive features of equal length positioned side-by-side at equal pitch'2011 8,035,133'Semiconductor device having two pairs of transistors of different types formed from shared linear-shaped conductive features with intervening transistors of common type on equal pitch'2011 8,030,689'Integrated circuit device and associated layout including separated diffusion regions of different type each having four gate electrodes with each of two complementary gate electrode pairs formed from respective linear conductive segment'2011 8,022,441'Semiconductor device and associated layouts having transistors formed from six linear conductive segments with gate electrode-to-gate electrode connection through single interconnect level and common node connection through different interconnect level'2011 7,994,545'Methods, structures, and designs for self-aligning local interconnects used in integrated circuits'2011 7,989,848'Semiconductor device having at least four side-by-side electrodes of equal length and equal pitch with at least two transistor connections to power or ground'2011 7,989,847'Semiconductor device having linear-shaped gate electrodes of different transistor types with uniformity extending portions of different lengths'2011 7,979,829'Integrated circuit cell library with cell-level process compensation technique (PCT) application and associated methods'2011 7,965,382'Methods and apparatus for multi-exposure patterning'2011 7,952,119'Semiconductor device and associated layout having three or more linear-shaped gate electrode level conductive segments of both equal length and equal pitch'2011 7,948,013'Semiconductor device and associated layouts having linear shaped gate electrodes defined along at least five adjacent gate electrode tracks of equal pitch'2011 7,948,012'Semiconductor device having 1965 nm gate electrode level region including at least four active linear conductive segments and at least one non-gate linear conductive segment'2011 7,943,966'Integrated circuit and associated layout with gate electrode level portion including at least two complimentary transistor forming linear conductive segments and at least one non-gate linear conductive segment'2011 7,943,967'Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments'2011 7,939,898'Diffusion variability control and transistor device sizing using threshold voltage implant'2011 7,932,544'Semiconductor device and associated layouts including linear conductive segments having non-gate extension portions'2011 7,932,545'Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers'2011 7,923,757'Semiconductor device and associated layouts having linear shaped gate electrodes defined along at least five adjacent gate electrode tracks of equal pitch with gate electrode connection through single interconnect level'2011 7,917,879'Semiconductor device with dynamic array section'2011 7,910,958'Semiconductor device and associated layouts having transistors formed from linear conductive segment with non-active neighboring linear conductive segment'2011 7,910,959'Semiconductor device and associated layouts having transistors formed from six linear conductive segments with gate electrode connection through single interconnect level'2011 7,906,801'Semiconductor device and associated layouts having transistors formed from six linear conductive segments with intervening diffusion contact restrictions'2011 7,908,578'Methods for designing semiconductor device with dynamic array section'2011 7,901,953'Methods and apparatus for detecting defects in interconnect structures'2011 7,888,705'Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same'2011 7,842,975'Dynamic array architecture'2010 7,763,534'Methods, structures and designs for self-aligning local interconnects used in integrated circuits'2010 7,590,968'Methods for risk-informed chip layout generation'2009 7,459,319'Method and apparatus for characterizing features formed on a substrate'2008 7,446,352'Dynamic array architecture'2008 7,332,360'Early detection of metal wiring reliability using a noise spectrum'2008 RE039697'Method of making floating-gate memory-cell array with digital logic transistors'2007 7,196,350'Method and apparatus for characterizing features formed on a substrate'2007 6,741,333'Multiple image photolithography system and method'2004 6,567,153'Multiple image photolithography system and method'2003 6,475,846'Method of making floating-gate memory-cell array with digital logic transistors'2002 6,262,914'Flash memory segmentation'2001 6,246,102'Integrated circuits, transistors, data processing systems, printed wiring boards, digital computers, smart power devices, and processes of manufacture'2001 6,191,976'Flash memory margin mode enhancements'2001 6,118,706'Flash memory block or sector clear operation'2000 6,060,372'Method for making a semiconductor device with improved sidewall junction capacitance'2000 5,942,374'Integrated circuits formed in radiation sensitive material and method of forming same'1999 5,917,222'Intergrated circuit combining high frequency bipolar and high power CMOS transistors'1999 5,911,104'Integrated circuit combining high frequency bipolar and high power CMOS transistors'1999 5,907,171'Method of making floating-gate memory-cell array with digital logic transistors'1999 5,874,849'Low voltage, high current pump for flash memory'1999 5,844,839'Programmable and convertible non-volatile memory array'1998 5,815,026'High efficiency, high voltage, low current charge pump'1998 5,811,850'LDMOS transistors, systems and methods'1998 5,801,091'Method for current ballasting and busing over active device area using a multi-level conductor process'1998 5,798,281'Method for stressing oxide in MOS devices during fabrication using first and second opposite potentials'1998 5,798,649'Method for detecting defects in semiconductor insulators'1998 5,767,551'Intergrated circuit combining high frequency bipolar and high power CMOS transistors'1998 5,732,021'Programmable and convertible non-volatile memory array'1998 5,717,634'Programmable and convertible non-volatile memory array'1998 5,715,195'Programmable memory verify \"0\" and verify \"1\" circuit and method'1998 5,703,807'EEPROM with enhanced reliability by selectable V.sub.PP for write and erase'1997 5,691,089'Integrated circuits formed in radiation sensitive material and method of forming same'1997 5,689,428'Integrated circuits, transistors, data processing systems, printed wiring boards, digital computers, smart power devices, and processes of manufacture'1997 5,681,768'Transistor having reduced hot carrier implantation'1997 5,679,968'Transistor having reduced hot carrier implantation'1997 5,677,041'Integrated circuits formed in radiation sensitive material and method of forming same'1997 5,665,991'Device having current ballasting and busing over active area using a multi-level conductor process'1997 5,656,517'Windowed source and segmented backgate contact linear geometry source cell for power DMOS processes'1997 5,648,275'Method for detecting defects in semiconductor insulators'1997 5,642,295'Systems utilizing a single chip microcontroller having non-volatile memory devices and power devices'1997 5,598,102'Method for detecting defects in semiconductor insulators'1997 5,589,697'Charge pump circuit with capacitors'1996 5,585,294'Method of fabricating lateral double diffused MOS (LDMOS) transistors'1996 5,585,657'Windowed and segmented linear geometry source cell for power DMOS processes'1996 5,567,550'Method of making a mask for making integrated circuits'1996 5,557,569'Low voltage flash EEPROM C-cell using fowler-nordheim tunneling'1996 5,515,319'Non-volatile memory cell and level shifter'1996 5,504,451'Gated thyristor and process for its simultaneous fabrication with high- and low-voltage semiconductor devices, integrated circuit containing the same, systems and methods.'1996 5,504,708'Flash EEPROM array with P-tank insulated from substrate by deep N-tank'1996 5,504,706'Low voltage Fowler-Nordheim flash EEPROM memory array utilizing single level poly cells'1996 5,500,392'Planar process using common alignment marks for well implants'1996 5,500,548'Non-epitaxial CMOS structures and processors'1996 5,491,105'LDMOS transistor with self-aligned source/backgate and photo-aligned gate'1996 5,479,040'Charge pump circuit with field oxide regions'1995 5,467,307'Memory array utilizing low voltage Fowler-Nordheim Flash EEPROM cell'1995 5,432,740'Low voltage flash EEPROM memory cell with merge select transistor and non-stacked gate structure'1995 5,429,959'Process for simultaneously fabricating a bipolar transistor and a field-effect transistor'1995 5,420,522'Method and system for fault testing integrated circuits using a light source'1995 5,411,908'Flash EEPROM array with P-tank insulated from substrate by deep N-tank'1995 5,407,844'Process for simultaneously fabricating an insulated gate field-effect transistor and a bipolar transistor'1995 5,382,536'Method of fabricating lateral DMOS structure'1995 5,364,801'Method of forming a charge pump circuit'1994 5,355,007'Devices for non-volatile memory, systems and methods'1994 5,349,225'Field effect transistor with a lightly doped drain'1994 5,348,895'LDMOS transistor with self-aligned source/backgate and photo-aligned gate'1994 5,319,564'Method and apparatus for integrated circuit design'1994 5,296,393'Process for the simultaneous fabrication of high-and-low-voltage semiconductor devices, integrated circuit containing the same, systems and methods'1994 5,275,961'Method of forming insulated gate field-effect transistors'1994 5,272,098'Vertical and lateral insulated-gate, field-effect transistors, systems and methods'1993 5,266,517'Method for forming a sealed interface on a semiconductor device'1993 5,245,543'Method and apparatus for integrated circuit design'1993 5,242,841'Method of making LDMOS transistor with self-aligned source/backgate and photo-aligned gate'1993 5,225,700'Circuit and method for forming a non-volatile memory cell'1993 5,204,541'Gated thyristor and process for its simultaneous fabrication with high- and low-voltage semiconductor devices'1993 5,157,281'Level-shifter circuit for integrated circuits'1992 5,145,798'Method of fabricating an insulated gate field effect transistor having lightly-doped source and drain extensions using an oxide sidewall spacer method'1992 5,023,690'Merged bipolar and complementary metal oxide semiconductor transistor device'1991 4,996,668'Erasable programmable memory'1991 4,939,558'EEPROM memory cell and driving circuitry'1990 4,912,676'Erasable programmable memory'1990 4,823,320'Electrically programmable fuse circuit for an integrated-circuit chip'1989 4,804,637'EEPROM memory cell and driving circuitry'1989 4,797,372'Method of making a merge bipolar and complementary metal oxide semiconductor transistor device'1989 4,742,492'EEPROM memory cell having improved breakdown characteristics and driving circuitry therefor'1988 4,736,342'Method of forming a field plate in a high voltage array'1988 4,718,041'EEPROM memory having extended life'1988 4,715,014'Modified three transistor EEPROM cell'1987 4,695,979'Modified four transistor EEPROM cell'1987 4,669,177'Process for making a lateral bipolar transistor in a standard CSAG process'1987 4,628,487'Dual slope, feedback controlled, EEPROM programming'1986 4,569,117'Method of making integrated circuit with reduced narrow-width effect'1986 4,566,175'Method of making insulated gate field effect transistor with a lightly doped drain using oxide sidewall spacer and double implantations'1986 4,268,179'Method and system for reproducing identification characters'1981

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1986–2007Patents assigned to TEXAS INSTRUMENTS INC (85)· patent assignee history

1986–2002Based in Missouri City, TX, US· patent location history

1989–1991Based in Freising, DE· patent location history

2000–2008Based in Sunnyvale, CA, US· patent location history

2008–2020Patents assigned to TELA INNOVATIONS INC (115)· patent assignee history

2008–2013Based in San Jose, CA, US· patent location history

2010–2021Based in Fremont, CA, US· patent location history

2011–2015Patents assigned to SMAYLING MICHAEL C (60)· patent assignee history

2011–2015Patents assigned to BECKER SCOTT T (59)· patent assignee history

2016–2021Patents assigned to MULTIBEAM CORP (20)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
TELA INNOVATIONS INC	115	2008–2020
TEXAS INSTRUMENTS INC	85	1986–2007
SMAYLING MICHAEL Cself	60	2011–2015
BECKER SCOTT T	59	2011–2015
MULTIBEAM CORP	20	2016–2021

Locations

Location	Patents	Span
Fremont, California, US	92	2010–2021
Missouri City, Texas, US	74	1986–2002
San Jose, California, US	45	2008–2013
Sunnyvale, California, US	9	2000–2008
Freising, DE	2	1989–1991