Inventor

Wei Zhao

Inventor

Fremont, CA, US

Overview

2014–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 36 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores35%

H01LSemiconductor devices19%

H10BElectronic memory devices18%

H10DInorganic electric semiconductor devices14%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%

G01RMeasuring electric variables1%

G06FElectric digital data processing1%

H10NElectric solid-state devices not otherwise provided for1%

PatentTitleYear

10,811,110Method of reducing injection type of program disturb during program pre-charge in memory device2020 10,790,003Maintaining channel pre-charge in program operation2020 10,770,157Method of reducing injection type of program disturb during program pre-charge in memory device2020 10,726,891Reducing post-read disturb in a nonvolatile memory device2020 10,685,978Three-dimensional memory device with drain-select-level isolation structures and method of making the same2020 10,685,979Three-dimensional memory device with drain-select-level isolation structures and method of making the same2020 10,685,723Reducing read disturb in two-tier memory device by modifying duration of channel discharge based on selected word line2020 10,636,488Multi-sensing scan for cross-temperature mitigation2020 10,636,494Apparatus and method for reducing noise generated from locked out sense circuits in a non-volatile memory system2020 10,636,500Reducing read disturb in two-tier memory device by modifying ramp up rate of word line voltages during channel discharge2020 10,629,272Two-stage ramp up of word line voltages in memory device to suppress read disturb2020 10,593,411Memory device with charge isolation to reduce injection type of program disturb2020 10,559,370System and method for in-situ programming and read operation adjustments in a non-volatile memory2020 10,510,385Write scheme for a static random access memory (SRAM)2019 10,249,372Reducing hot electron injection type of read disturb in 3D memory device during signal switching transients2019 10,068,651Channel pre-charge to suppress disturb of select gate transistors during erase in memory2018 9,761,320'Reducing hot electron injection type of read disturb during read recovery phase in 3D memory'2017 9,728,258'Ternary content addressable memory'2017 9,640,273'Mitigating hot electron program disturb'2017 9,530,785'Three-dimensional memory devices having a single layer channel and methods of making thereof'2016 9,530,790'Three-dimensional memory device containing CMOS devices over memory stack structures'2016 9,515,079'Three dimensional memory device with blocking dielectric having enhanced protection against fluorine attack'2016 9,502,471'Multi tier three-dimensional memory devices including vertically shared bit lines'2016 9,406,391'Method of reducing hot electron injection type of read disturb in dummy memory cells'2016 9,378,832'Method to recover cycling damage and improve long term data retention'2016 9,361,993'Method of reducing hot electron injection type of read disturb in memory'2016 9,336,891'Look ahead read method for non-volatile memory'2016 9,312,010'Programming of drain side word line to reduce program disturb and charge loss'2016 9,305,849'Method of making a three dimensional NAND device'2016 9,286,994'Method of reducing hot electron injection type of read disturb in dummy memory cells'2016 9,236,131'Bias to detect and prevent short circuits in three-dimensional memory device'2016 9,236,396'Three dimensional NAND device and method of making thereof'2016 9,230,982'Protective structure to prevent short circuits in a three-dimensional memory device'2016 9,177,966'Three dimensional NAND devices with air gap or low-k core'2015 9,129,710'Dynamic trim method for non volatile memory products'2015 8,630,137'Dynamic trim method for non-volatile memory products'2014

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2014–2015Patents assigned to MAXIM INTEGRATED PRODUCTS (2)· patent assignee history

2014Patents assigned to BERGEMONT ALBERT (1)· patent assignee history

2014–2020Based in Fremont, CA, US· patent location history

2015–2016Patents assigned to SANDISK TECHNOLOGIES INC (15)· patent assignee history

2015–2016Based in Milpitas, CA, US· patent location history

2015–2020Based in San Jose, CA, US· patent location history

2016–2020Patents assigned to SANDISK TECHNOLOGIES LLC (20)· patent assignee history

2017Based in New Taipei, TW· patent location history

2019Based in Shanghai, CN· patent location history

2020Patents assigned to WESTERN DIGITAL TECH INC (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
SANDISK TECHNOLOGIES LLC	20	2016–2020
SANDISK TECHNOLOGIES INC	15	2015–2016
MAXIM INTEGRATED PRODUCTS	2	2014–2015
WESTERN DIGITAL TECH INC	2	2020
BERGEMONT ALBERT	1	2014

Locations

Location	Patents	Span
Fremont, California, US	23	2014–2020
Milpitas, California, US	7	2015–2016
San Jose, California, US	4	2015–2020
Shanghai, CN	1	2019
New Taipei, TW	1	2017