Inventor

Bhyrav M. Mutnury

Inventor

Austin, TX, US

Overview

2008–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 190 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H05Kprimary

H05KPrinted circuits20%

G06FElectric digital data processing17%

H04LTransmission of digital information, e.g. telegraphic communication12%

Y10TTechnical subjects covered by former us classification8%

G01RMeasuring electric variables6%

H01RElectrically-conductive connections6%

H04BTransmission5%

G11CStatic stores5%

H01BCables4%

H01PWaveguides3%

PatentTitleYear

11,068,778System and method for optimizing the design of circuit traces in a printed circuit board for high speed communications2021 11,026,321Information handling system comprising a processor coupled to a board and including a differential trace pair having a first straight differential trace and a second serpentine shape differential trace2021 11,010,250Memory device failure recovery system2021 10,993,312System and method for ground via optimization for high speed serial interfaces2021 10,950,369Inverted cable design for high-speed, low loss signal transmission2021 10,930,410Flat flexible cable with bonded ground wires and method for forming same2021 10,925,153System and method to provide connection pads for high speed cables2021 10,912,190Electrical connector element2021 10,904,998System and method for via optimization in a printed circuit board2021 10,897,813Differential trace pair system2021 10,862,232Circuit board pad connector system2020 10,860,505System and method for enhancing receiver equalization2020 10,856,414System and method for minimizing connector pad open-circuit stubs2020 10,856,411System and method for design of high speed signaling and power delivery2020 10,842,017Printed circuit boards with non-functional features2020 10,813,211Printed circuit board layout for mitigating near-end crosstalk2020 10,806,024Method of utilizing serpentine regions2020 10,795,592System and method for setting communication channel equalization of a communication channel between a processing unit and a memory2020 10,779,404Circuit board pad resonance control system2020 10,762,031System and method for setting equalization for communication between a processor and a device2020 10,736,216Non-rectangular connection pad for improved electrical characteristics on traces2020 10,735,227System and method to monitor component wear on high speed serial interfaces2020 10,700,459Circuit board flex cable system2020 10,698,855Differential pair contact resistance asymmetry compensation system2020 10,685,736Maintaining highest performance of DDR5 channel with marginal signal integrity2020 10,667,393Stepped vias for next generation speeds2020 10,657,009System and method to dynamically increase memory channel robustness at high transfer rates2020 10,660,197Differential pair group equalization system2020 10,660,206Information handling system interposer enabling specialty processor integrated circuit in standard sockets2020 10,644,907System and method of variable equalization for crosstalk minimization2020 10,643,766Drain-aligned cable and method for forming same2020 10,617,003Method for manufacturing a surface mount technology (SMT) pad structure for next generation speeds2020 10,605,585Systems and methods for frequency shifting resonance of an unused via in a printed circuit board2020 10,609,814Differential trace pair system2020 10,595,397Structure to dampen barrel resonance of unused portion of printed circuit board via2020 10,595,396System and method of utilizing serpentine regions2020 10,579,517System and method for providing per channel frequency optimization in a double data rate memory system2020 10,581,652System and method for PAM-4 transmitter bit equalization for improved channel performance beyond 32 Gbps2020 10,560,290Information handling system half unit interval equalization2020 10,522,930Systems and methods for frequency shifting resonance of connector stubs2019 10,515,300High speed serial links for high volume manufacturing2019 10,496,477System and method of utilizing memory modules2019 10,499,492Stubbed differential trace pair system2019 10,492,290Circuit board pad mounting orientation system2019 10,485,096Differential trace pair system2019 10,474,384System and method for providing a back door communication path between channels on dual-channel DIMMs2019 10,469,291System and method to optimize equalization coefficients in a high-speed serial interface2019 10,430,363Systems and methods of in-situ digital eye characterization for serial data transmitter circuitry2019 10,424,420Drain aligned cable for next generation speeds2019 10,405,425Surface mount technology (SMT) pad design with differential contact strips having converging narrowing distal ends that facilitate high speed communication2019 10,396,760Differential pair contact resistance asymmetry compensation system2019 10,394,725System and method for device assembly based on component characteristics stored with the components2019 10,381,137System and method for mitigating signal propagation skew between signal conducting wires of a signal conducting cable2019 10,368,437Cable assembly for an information handling system2019 10,355,890Repeatable backchannel link adaptation for high speed serial interfaces2019 10,339,088System and method to blacklist equalization coefficients in a high-speed serial interface2019 10,325,043Time domain response simulation system2019 10,319,454System and method for simulating a memory technology2019 10,303,642System and method for communicating over a connector device based on component characteristics stored with the components of the connector device2019 10,306,749System and method of utilizing serpentine regions2019 10,298,420System and method to enhance feed-forward equalization in a high-speed serial interface2019 10,298,421Power aware receiver/transmitter adaptation for high speed serial interfaces2019 10,296,481Adapter board system2019 10,299,370Differential trace pair system2019 10,292,266Surface mount connector pad2019 10,257,931Systems and methods for providing grooved vias in high-speed printed circuit boards2019 10,229,018System and method for data restore flexibility on dual channel NVDIMMs2019 10,229,081System level crosstalk mitigation2019 10,201,084Printed circuit board via design2019 10,141,086Cable for high speed data communications2018 10,135,170Contact geometry for contacts in high speed data connectors2018 10,126,110Systems and methods for frequency shifting resonance of an unused via in a printed circuit board2018 10,128,903System and method of cancelling floquet mode resonance and far end crosstalk, and mitigating crosstalk in a printed circuit board2018 10,122,122Printed circuit board connector with cross-talk mitigation2018 10,111,334Information handling system interposer enabling specialty processor integrated circuit in standard sockets2018 10,103,910Pulse amplitude modulation equalization optimization system2018 10,054,979Placement of ground vias for high-speed differential signals2018 9,996,646System and method of determining high speed resonance due to coupling from broadside layers2018 9,985,360Electrical connector for an information handling system2018 9,986,651Method for mitigating signal attenuation in printed circuit board connections2018 9,984,741System and method of transferring data over available pins2018 9,980,378Surface mount connector pad2018 9,954,576System and method for PAM-4 transmitter bit equalization for improved channel performance2018 9,955,568Structure to dampen barrel resonance of unused portion of printed circuit board via2018 9,946,321System and method to proactively screen component wear through time domain response profiling2018 9,940,582Intelligent problem tracking electronic system for optimizing technical support2018 9,935,682System and method for PAM-4 transmitter bit equalization for improved channel performance2018 9,930,771'Aperiodic routing to mitigate floquet mode resonances'2018 9,929,856'System and method for jitter negation in a high speed serial interface'2018 9,923,740'System aware transmitter adaptation for high speed serial interfaces'2018 9,847,602Shielded high speed connector with reduced crosstalk2017 9,825,730'System and method for optimizing link performance with lanes operating at different speeds'2017 9,785,607'In-situ die-to-die impedance estimation for high-speed serial links'2017 9,781,825'Flex circuit, an information handling system, and a method of manufacturing a flexible circuit'2017 9,772,913'System and method of read/write control for dual channel memory modules for robust performance'2017 9,769,926'Breakout via system'2017 9,768,555'Systems and methods for frequency shifting resonance of connector stubs'2017 9,762,418'Repeatable backchannel link adaptation for high speed serial interfaces'2017 9,742,464'Apparatus and method for semi-circular routing for transmission line signals'2017 9,728,236'System and method of training optimization for dual channel memory modules'2017 9,692,620'System aware transmitter adaptation for high speed serial interfaces'2017 9,678,137'System and method to monitor contact joint integrity'2017 9,673,931'System and method of selective encoding for enhanced serializer/deserializer throughput'2017 9,674,013'Enhanced receiver equalization'2017 9,647,852'Selective single-ended transmission for high speed serial links'2017 9,634,777'Systems and methods for measurement of electrical channel loss'2017 9,589,701'Dual axial cable'2017 9,583,845'Electrical connector for an information handling system'2017 9,563,384'Systems and methods for data alignment in a memory system'2017 9,537,618'Systems and methods for differential pair in-pair skew determination and compensation'2017 9,531,569'Power aware receiver/transmitter adaptation for high speed serial interfaces'2016 9,509,532'Duty-cycled equalizations'2016 9,431,733'Double action compliant connector pin'2016 9,417,802'Systems and methods for data alignment in a memory system'2016 9,363,026'Systems and methods for measurement of electrical channel loss'2016 9,338,881'Manufacturing a printed circuit board with reduced dielectric loss'2016 9,325,536'Enhanced receiver equalization'2016 9,317,649'System and method of determining high speed resonance due to coupling from broadside layers'2016 9,313,056'System aware transmitter adaptation for high speed serial interfaces'2016 9,244,120'Simulation of printed circuit board impedance variations and crosstalk effects'2016 9,218,309'Systems and methods for impedance matching for multi-drop topologies'2015 9,210,007'Duty-cycled equalization'2015 9,178,626'System and method of enhancing signal integrity'2015 9,159,470'Dual axial cable'2015 9,146,271'Identifying a signal on a printed circuit board under test'2015 9,119,334'Method for manufacturing circuit board having holes to increase resonant frequency of via stubs'2015 9,087,029'Qualifying circuit board materials'2015 9,024,208'Systems and methods for frequency shifting resonance of an unused via in a printed circuit board'2015 8,901,946'Identifying a signal on a printed circuit board under test'2014 8,830,690'Minimizing plating stub reflections in a chip package using capacitance'2014 8,639,545'Generating an optimized analytical business transformation'2014 8,570,816'Digital memory system that dynamically adjusts reference voltage as a function of traffic intensity'2013 8,569,873'Mitigation of plating stub resonance by controlling surface roughness'2013 8,572,004'Space solution search'2013 8,564,322'Receiver signal probing using a shared probe point'2013 8,558,567'Identifying a signal on a printed circuit board under test'2013 8,552,291'Cable for high speed data communications'2013 8,542,494'Circuit board having holes to increase resonant frequency of via stubs'2013 8,514,215'Dynamically managing power consumption of a computer with graphics adapter configurations'2013 8,494,038'Common mode noise reduction within differential signal'2013 8,492,658'Laminate capacitor stack inside a printed circuit board for electromagnetic compatibility capacitance'2013 8,456,928'Dynamic adjustment of reference voltage in a computer memory system'2013 8,453,081'Electrical design space exploration'2013 8,402,406'Controlling plating stub reflections in a chip package'2013 8,390,393'Pre-distortion based impedence discontinuity remediation for via stubs and connectors in printed circuit board design'2013 8,359,220'Technical support routing among members of a technical support group'2013 8,325,459'Channel performance of electrical lines'2012 8,327,196'Identifying an optimized test bit pattern for analyzing electrical communications channel topologies'2012 8,319,113'Printed circuit board with reduced dielectric loss'2012 8,310,885'Measuring SDRAM control signal timing'2012 8,289,043'Simulation of printed circuit board impedance variations and crosstalk effects'2012 8,289,101'Pre-distortion based impedence discontinuity remediation for via stubs and connectors in printed circuit board design'2012 8,275,644'Generating an optimized analytical business transformation'2012 8,276,106'Swarm intelligence for electrical design space modeling and optimization'2012 8,269,505'Locating short circuits in printed circuit boards'2012 8,242,784'Qualifying circuit board materials'2012 8,239,403'Enhancing soft file system links'2012 8,201,133'Printed circuit board with reduced signal distortion'2012 8,165,311'Airflow optimization and noise reduction in computer systems'2012 8,140,441'Workflow management in a global support organization'2012 8,110,500'Mitigation of plating stub resonance by controlling surface roughness'2012 8,106,666'Testing an electrical component'2012 8,102,042'Reducing plating stub reflections in a chip package using resistive coupling'2012 8,084,692'Reducing noise coupling in high speed digital systems'2011 8,086,896'Dynamically tracking virtual logical storage units'2011 7,999,185'Transmission cable with spirally wrapped shielding'2011 7,987,110'Managing organizational resources'2011 7,977,574'Cable for high speed data communications'2011 7,944,963'Method and apparatus for jitter compensation in receiver circuits using nonlinear dynamic phase shifting technique based on bit history pattern'2011 7,868,651'Off-die termination of memory module signal lines'2011 7,868,652'Off-die termination module with a spring loaded pin in a DIMM socket'2011 7,813,447'Apparatus, system, and method for dynamic phase equalization in a communication channel'2010 7,791,227'Electromagnetic morphing apparatus for hot pluggable architected systems'2010 7,759,958'Apparatus, system, and method for integrated component testing'2010 7,739,562'Programmable diagnostic memory module'2010 7,730,369'Method for performing memory diagnostics using a programmable diagnostic memory module'2010 7,725,783'Method and apparatus for repeatable drive strength assessments of high speed memory DIMMs'2010 7,701,222'Method for validating printed circuit board materials for high speed applications'2010 7,696,787'Signal history controlled slew-rate transmission method and bus interface transmitter'2010 7,649,142'Cable for high speed data communications'2010 7,533,458'Method for reducing noise coupling in high speed digital systems'2009 7,531,749'Cable for high speed data communications'2009 7,525,045'Cable for high speed data communications'2009 7,525,319'Method and apparatus to electrically qualify high speed PCB connectors'2009 7,479,597'Conductor cable having a high surface area'2009 7,479,601'High-speed cable having increased current return uniformity and method of making same'2009 7,474,117'Bi-directional universal serial bus booster circuit'2009 7,443,180'On-chip probing apparatus'2008 7,394,281'Bi-directional universal serial bus booster circuit'2008 7,352,211'Signal history controlled slew-rate transmission method and bus interface transmitter'2008

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2008–2018Patents assigned to IBM (62)· patent assignee history

2008–2021Based in Austin, TX, US· patent location history

2011–2018Patents assigned to MUTNURY BHYRAV M (40)· patent assignee history

2011–2018Patents assigned to CASES MOISES (26)· patent assignee history

2012–2016Patents assigned to RODRIGUES TERENCE (15)· patent assignee history

2015–2021Patents assigned to DELL PRODUCTS LP (120)· patent assignee history

2015–2021Based in Round Rock, TX, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
DELL PRODUCTS LP	120	2015–2021
IBM	62	2008–2018
MUTNURY BHYRAV Mself	40	2011–2018
CASES MOISES	26	2011–2018
RODRIGUES TERENCE	15	2012–2016

Locations

Location	Patents	Span
Austin, Texas, US	112	2008–2021
Round Rock, Texas, US	78	2015–2021