Inventor

Trung T. Doan

Inventor
Boise, ID, US

Overview

432→
Patents
1990–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 432 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1016%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1015%
H10DInorganic electric semiconductor devices13%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests9%
C23CCoating metallic material6%
H10BElectronic memory devices6%
B24BMachines, devices, or processes for grinding or polishing6%
H10HInorganic light-emitting semiconductor devices having potential barriers4%
H10NElectric solid-state devices not otherwise provided for2%
B23QDetails, components, or accessories for machine tools, e.g. arrangements for copying or controlling2%
PatentTitleYear
10,766,117Retaining ring with shaped surface20209,937,601Retaining ring with Shaped Surface20189,231,152'Light emitting diode'20169,214,456'Light emitting diode (LED) system having lighting device and wireless control system'20159,190,589'Light emitting diode'20159,186,773'Retaining ring with shaped surface'20158,933,467'Smart integrated semiconductor light emitting system including nitride based light emitting diodes (LED) and application specific integrated circuits (ASIC)'20158,921,204'Method for fabricating semiconductor dice by separating a substrate from semiconductor structures using multiple laser pulses'20148,871,547'Method for fabricating vertical light emitting diode (VLED) structure using a laser pulse to remove a carrier substrate'20148,835,953'Lighting device comprising LEDs with phosphor layers'20148,802,465'Method for handling a semiconductor wafer assembly'20148,802,469'Method of fabricating semiconductor die using handling layer'20148,778,780'Method for defining semiconductor devices'20148,759,128'Light emitting diode (LED) die having recessed electrode and light extraction structures and method of fabrication'20148,723,160'Light emitting diode (LED) die having peripheral electrode frame and method of fabrication'20148,716,041'Method for fabricating side by side light emitting diode (LED) having separate electrical and heat transfer paths'20148,685,764'Method to make low resistance contact'20148,680,534'Vertical light emitting diodes (LED) having metal substrate and spin coated phosphor layer for producing white light'20148,614,449'Protection for the epitaxial structure of metal devices'20138,585,468'Retaining ring with shaped surface'20138,552,458'Side by side light emitting diode (LED) having separate electrical and heat transfer paths'20138,552,451'Light-emitting diode with increased light extraction'20138,518,184'Methods and systems for controlling temperature during microfeature workpiece processing, E.G., CVD deposition'20138,507,302'Wall structures for a semiconductor wafer'20138,434,883'LLB bulb having light extracting rough surface pattern (LERSP) and method of fabrication'20138,410,508'Light emitting diode (LED) package having wavelength conversion member and wafer level fabrication method'20138,384,192'Methods for forming small-scale capacitor structures'20138,319,252'Light emitting device with high color rendering index and high luminescence efficiency'20128,318,519'Method for handling a semiconductor wafer assembly'20128,283,652'Vertical light emitting diode (VLED) die having electrode frame and method of fabrication'20128,143,112'Method for removing semiconductor street material'20128,124,454'Die separation'20128,124,491'Container capacitor structure and method of formation thereof'20128,097,514'Method for an integrated circuit contact'20128,084,780'Smart integrated semiconductor light emitting system including light emitting diodes and application specific integrated circuits (ASIC)'20118,066,551'Retaining ring with shaped surface'20118,034,716'Semiconductor structures including vertical diode structures and methods for making the same'20118,012,774'Coating process for a light-emitting diode (LED)'20118,008,678'Light-emitting diode with increased light extraction'20117,968,379'Method of separating semiconductor dies'20117,964,436'Co-sputter deposition of metal-doped chalcogenides'20117,956,396'Memory array having floating gate semiconductor device'20117,944,025'Semiconductor constructions'20117,935,950'Controllable ovonic phase-change semiconductor memory device and methods of programming the same'20117,927,190'Retaining ring with shaped surface'20117,906,393'Methods for forming small-scale capacitor structures'20117,892,891'Die separation'20117,871,934'Method for an integrated circuit contact'20117,852,015'Solid state lighting system and maintenance method therein'20107,829,440'Method of separating semiconductor dies'20107,807,503'Die-wafer package and method of fabricating same'20107,776,647'Semiconductor components and methods of fabrication with circuit side contacts, conductive vias and backside conductors'20107,771,537'Methods and systems for controlling temperature during microfeature workpiece processing, E.G. CVD deposition'20107,723,718'Epitaxial structure for metal devices'20107,687,322'Method for removing semiconductor street material'20107,656,012'Apparatus for use in semiconductor wafer processing for laterally displacing individual semiconductor devices away from one another'20107,647,886'Systems for depositing material onto workpieces in reaction chambers and methods for removing byproducts from reaction chambers'20107,646,033'Systems and methods for producing white-light light emitting diodes'20107,629,195'Method of making light emitting diodes (LEDs) with improved light extraction by roughening'20097,625,795'Container capacitor structure and method of formation thereof'20097,625,694'Selective provision of a diblock copolymer material'20097,588,677'Methods and apparatus for electrical, mechanical and/or chemical removal of conductive material from a microelectronic substrate'20097,579,235'Container capacitor structure and method of formation thereof'20097,576,012'Atomic layer deposition methods'20097,569,485'Method for an integrated circuit contact'20097,563,625'Method of making light-emitting diodes (LEDs) with improved light extraction by roughening'20097,563,666'Semiconductor structures including vertical diode structures and methods of making the same'20097,530,153'Attaching components of a carrier head'20097,528,430'Electronic systems'20097,504,008'Refurbishment of sputtering targets'20097,485,961'Approach to avoid buckling in BPSG by using an intermediate barrier layer'20097,482,702'Semiconductor component sealed on five sides by polymer sealing layer'20097,473,936'Light emitting diodes (LEDs) with improved light extraction by roughening'20097,473,582'Method for fabricating semiconductor component with thinned substrate having pin contacts'20097,470,344'Chemical dispensing system for semiconductor wafer processing'20087,465,406'Method of exposing a substrate to a surface microwave plasma, etching method, deposition method, surface microwave plasma generating apparatus, semiconductor substrate etching apparatus, semiconductor substrate deposition apparatus, and microwave plasma generating antenna assembly'20087,452,739'Method of separating semiconductor dies'20087,446,393'Co-sputter deposition of metal-doped chalcogenides'20087,432,119'Light emitting diode with conducting metal substrate'20087,431,773'Atomic layer deposition apparatus and method'20087,432,600'System having semiconductor component with multiple stacked dice'20087,432,604'Semiconductor component and system having thinned, encapsulated dice'20087,422,635'Methods and apparatus for processing microfeature workpieces, e.g., for depositing materials on microfeature workpieces'20087,417,325'Semiconductor component having thinned die with conductive vias configured as conductive pin terminal contacts'20087,413,918'Method of making a light emitting diode'20087,413,928'Die-wafer package and method of fabricating same'20087,405,438'Capacitor constructions and semiconductor structures'20087,402,518'Atomic layer deposition methods'20087,388,294'Semiconductor components having stacked dice'20087,382,060'Semiconductor component having thinned die, polymer layers, contacts on opposing sides, and conductive vias connecting the contacts'20087,378,288'Systems and methods for producing light emitting diode array'20087,368,014'Variable temperature deposition methods'20087,367,871'Semiconductor processing methods of removing conductive material'20087,344,434'Retaining ring with shaped surface'20087,344,755'Methods and apparatus for processing microfeature workpieces; methods for conditioning ALD reaction chambers'20087,335,994'Semiconductor component having multiple stacked dice'20087,323,739'Semiconductor device having recess and planarized layers'20087,323,230'Coating for aluminum component'20087,315,082'Semiconductor device having integrated circuit contact'20087,282,440'Integrated circuit contact'20077,282,447'Method for an integrated circuit contact'20077,279,725'Vertical diode structures'20077,279,041'Atomic layer deposition methods and atomic layer deposition tools'20077,279,398'Microfeature workpiece processing apparatus and methods for controlling deposition of materials on microfeature workpieces'20077,276,448'Method for an integrated circuit contact'20077,270,596'Chemical mechanical polishing process'20077,268,382'DRAM cells'20077,258,892'Methods and systems for controlling temperature during microfeature workpiece processing, e.g., CVD deposition'20077,253,430'Controllable ovonic phase-change semiconductor memory device'20077,247,944'Connector assembly'20077,247,581'Methods for treating pluralities of discrete semiconductor substrates'20077,235,138'Microfeature workpiece processing apparatus and methods for batch deposition of materials on microfeature workpieces'20077,224,065'Contact/via force fill techniques and resulting structures'20077,220,670'Method of producing rough polysilicon by the use of pulsed plasma chemical vapor deposition and products produced by same'20077,221,059'Wafer level semiconductor component having thinned, encapsulated dice and polymer dam'20077,220,312'Methods for treating semiconductor substrates'20077,202,104'Co-sputter deposition of metal-doped chalcogenides'20077,195,944'Systems and methods for producing white-light emitting diodes'20077,186,580'Light emitting diodes (LEDs) with improved light extraction by roughening'20077,183,208'Methods for treating pluralities of discrete semiconductor substrates'20077,169,691'Method of fabricating wafer-level packaging with sidewall passivation and related apparatus'20077,170,103'Wafer with vertical diode structures'20077,166,875'Vertical diode structures'20077,160,785'Container capacitor structure and method of formation thereof'20077,157,353'Method for fabricating encapsulated semiconductor components'20077,153,410'Methods and apparatus for electrochemical-mechanical processing of microelectronic workpieces'20067,132,731'Semiconductor component and assembly having female conductive members'20067,122,906'Die-wafer package and method of fabricating same'20067,115,529'Atomic layer deposition methods'20067,112,544'Method of atomic layer deposition on plural semiconductor substrates simultaneously'20067,112,121'Methods and apparatus for electrical, mechanical and/or chemical removal of conductive material from a microelectronic substrate'20067,101,594'Methods of forming capacitor constructions'20067,097,782'Method of exposing a substrate to a surface microwave plasma, etching method, deposition method, surface microwave plasma generating apparatus, semiconductor substrate etching apparatus, semiconductor substrate deposition apparatus, and microwave plasma generating antenna assembly'20067,081,665'Semiconductor component having thinned substrate, backside pin contacts and circuit side contacts'2006RE039195'Polishing pad refurbisher for in situ, real-time conditioning and cleaning of a polishing pad used in chemical-mechanical polishing of microelectronic substrates'20067,078,266'Method for fabricating semiconductor components with thinned substrate, back side contacts and circuit side contacts'2006RE039126'Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs'20067,056,194'Semiconductor processing methods of removing conductive material'20067,056,806'Microfeature workpiece processing apparatus and methods for controlling deposition of materials on microfeature workpieces'20067,049,238'Method for fabricating semiconductor device having recess'20067,029,949'Method for fabricating encapsulated semiconductor components having conductive vias'20067,030,037'Atomic layer deposition apparatus and method'20067,022,605'Atomic layer deposition methods'20067,012,010'Methods of forming trench isolation regions'20067,009,298'Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer'20067,001,845'Methods of treating surfaces of substrates'20067,001,251'Method and apparatus for releasably attaching a polishing pad to a chemical-mechanical planarization machine'20067,001,481'Method and system providing high flux of point of use activated reactive species for semiconductor processing'20066,977,097'Particle forming methods'20056,974,367'Chemical mechanical polishing process'20056,964,915'Method of fabricating encapsulated semiconductor components by etching'20056,956,210'Methods for preparing samples for atom probe analysis'20056,953,743'Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer'20056,949,464'Contact/via force fill techniques'20056,945,857'Polishing pad conditioner and methods of manufacture and recycling'20056,916,723'Methods of forming rugged semiconductor-containing surfaces'20056,916,374'Atomic layer deposition methods and atomic layer deposition tools'20056,914,310'Semiconductor isolator system'20056,908,784'Method for fabricating encapsulated semiconductor components'20056,903,442'Semiconductor component having backside pin contacts'20056,903,010'Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer'20056,897,467'Controllable ovanic phase-change semiconductor memory device'20056,893,506'Atomic layer deposition apparatus and method'20056,893,333'Chemical mechanical polishing slurry'20056,890,790'Co-sputter deposition of metal-doped chalcogenides'20056,885,051'Minimally spaced MRAM structures'20056,881,667'Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer'20056,881,974'Probe card for testing microelectronic components'20056,882,033'High density direct connect LOC assembly'20056,863,725'Method of forming a Ta2O5 comprising layer'20056,861,351'Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer'20056,847,535'Removable programmable conductor memory card and associated read/write device and method of operation'20056,846,739'MOCVD process using ozone as a reactant to deposit a metal oxide barrier layer'20056,835,674'Methods for treating pluralities of discrete semiconductor substrates'20046,831,324'Method of producing rough polysilicon by the use of pulsed plasma chemical vapor deposition and products produced by the same'20046,828,175'Semiconductor component with backside contacts and method of fabrication'20046,828,812'Test apparatus for testing semiconductor dice including substrate with penetration limiting contacts for making electrical connections'20046,825,107'Method for fabricating a memory chip'20046,803,073'Particle forming method'20046,800,517'Methods of forming conductive interconnects'20046,793,736'Method of providing high flux of point of use activated reactive species for semiconductor processing'20046,793,764'Chemical dispensing system for semiconductor wafer processing'20046,790,130'Semiconductor processing methods of removing conductive material'20046,787,401'Method of making vertical diode structures'20046,784,046'Method of making vertical diode structures'20046,781,145'Controlable ovonic phase-change semiconductor memory device'20046,780,740'Method for fabricating a floating gate semiconductor device'20046,773,938'Probe card, e.g., for testing microelectronic components, and methods for making same'20046,765,250'Self-aligned, trenchless mangetoresitive random-access memory (MRAM) structure with sidewall containment of MRAM structure'20046,764,956'Methods of treating dielectric materials'20046,753,565'Container capacitor array having a common top capacitor plate'20046,750,069'Minimally spaced MRAM structures'20046,750,089'Methods of forming conductive interconnects'20046,750,091'Diode formation method'20046,746,934'Atomic layer doping apparatus and method'20046,743,699'Method of fabricating semiconductor components'20046,743,724'Planarization process for semiconductor substrates'20046,739,944'System for real-time control of semiconductor wafer polishing'20046,740,552'Method of making vertical diode structures'20046,734,121'Methods of treating surfaces of substrates'20046,730,954'Method of depositing tungsten nitride using a source gas comprising silicon'20046,720,272'Methods of forming capacitor constructions'20046,719,012'Method of forming trench isolation regions'20046,693,319'Container capacitor structure and method of formation thereof'20046,689,624'Method of forming self-aligned, trenchless mangetoresitive random-access memory (MRAM) structure with sidewall containment of MRAM structure'20046,690,044'Approach to avoid buckling BPSG by using an intermediate barrier layer'20046,689,661'Method for forming minimally spaced MRAM structures'20046,683,005'Method of forming capacitor constructions'20046,682,943'Method for forming minimally spaced MRAM structures'20046,663,470'Method and apparatus for releasably attaching a polishing pad to a chemical-mechanical planarization machine'20036,661,051'Container capacitor structure and method of formation thereof'20036,653,154'Method of forming self-aligned, trenchless mangetoresistive random-access memory (MRAM) structure with sidewall containment of MRAM structure'20036,653,220'Advance metallization process'20036,645,844'Methods for high density direct connect LOC assembly'20036,632,736'Method of forming low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer'20036,628,410'Endpoint detector and method for measuring a change in wafer thickness in chemical-mechanical polishing of semiconductor wafers and other microelectronic substrates'20036,624,517'Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer'20036,620,680'Method of forming a contact structure and a container capacitor structure'20036,613,702'Methods of forming capacitor constructions'20036,608,342'Container capacitor structure and method of formation thereof'20036,602,380'Method and apparatus for releasably attaching a polishing pad to a chemical-mechanical planarization machine'20036,585,575'Method and apparatus for releasably attaching a polishing pad to a chemical-mechanical planarization machine'20036,582,281'Semiconductor processing methods of removing conductive material'20036,583,028'Methods of forming trench isolation regions'20036,573,199'Methods of treating dielectric materials with oxygen, and methods of forming capacitor constructions'20036,573,601'Integrated circuit contact'20036,559,054'Methods of treating surfaces of substrates'20036,551,893'Atomic layer deposition of capacitor dielectric'20036,541,353'Atomic layer doping apparatus and method'20036,537,915'Methods of treating surfaces of substrates'20036,531,401'Method of cleaning a substrate surface using a frozen material'20036,531,352'Methods of forming conductive interconnects'20036,531,761'High density direct connect LOC assembly'20036,528,834'Container capacitor structure and method of formation thereof'20036,525,366'Uniform dielectric layer and method to form same'20036,521,931'Self-aligned, magnetoresitive random-access memory (MRAM) structure utilizing a spacer containment scheme'20036,514,125'Method and apparatus for releasably attaching a polishing pad to a chemical-mechanical planarization machine'20036,506,101'Method and apparatus for releasably attaching a polishing pad to a chemical-mechanical planarization machine'20036,488,566'System for real-time control of semiconductor wafer polishing'20026,482,077'Method and apparatus for releasably attaching a polishing pad to a chemical-mechanical planarization machine'20026,472,756'Method of forming titanium silicide and titanium by chemical vapor deposition and resulting apparatus'20026,472,323'Method of depositing tungsten nitride using a source gas comprising silicon'20026,472,320'Method of producing rough polysilicon by the use of pulsed plasma chemical vapor deposition and products produced by the same'20026,464,561'System for real-time control of semiconductor wafer polishing'20026,464,560'System for real-time control of semiconductor wafer polishing'20026,464,564'System for real-time control of semiconductor wafer polishing'20026,440,613'Method of fabricating attenuated phase shift mask'20026,429,086'Method of depositing tungsten nitride using a source gas comprising silicon'20026,423,621'Controllable ovonic phase-change semiconductor memory device and methods of fabricating the same'20026,420,249'Method for fabricating a floating gate semiconductor device'20026,414,392'Integrated circuit contact'20026,395,628'Contact/via force fill techniques'20026,395,600'Method of forming a contact structure and a container capacitor structure'20026,391,778'Contact/via force fill techniques and resulting structures'20026,391,735'Container capacitor structure'20026,388,284'Capacitor structures'20026,376,369'Robust pressure aluminum fill process'20026,358,756'Self-aligned, magnetoresistive random-access memory (MRAM) structure utilizing a spacer containment scheme'20026,350,638'Method of forming complementary type conductive regions on a substrate'20026,340,624'Method of forming a circuitry isolation region within a semiconductive wafer'20026,340,894'Semiconductor testing apparatus including substrate with contact members and conductive polymer interconnect'20026,338,667'System for real-time control of semiconductor wafer polishing'20026,335,225'High density direct connect LOC assembly'20026,333,240'Method of spacing a capacitor from a contact site'20016,331,488'Planarization process for semiconductor substrates'20016,329,263'Method of forming a container capacitor structure'20016,329,666'Controllable ovonic phase-change semiconductor memory device and methods of fabricating the same'20016,323,540'Semiconductor processing method of forming a contact opening to a region adjacent a field isolation mass, and a semiconductor structure'20016,323,101'Semiconductor processing methods, methods of forming silicon dioxide methods of forming trench isolation regions, and methods of forming interlevel dielectric layers'20016,323,138'Capacitor, methods of forming capacitors, methods for forming silicon nitride layers on silicon-comprising substrates, and methods of densifying silicon nitride layers'20016,306,009'System for real-time control of semiconductor wafer polishing'20016,303,953'Integrated capacitor bottom electrode with etch stop layer'20016,301,006'Endpoint detector and method for measuring a change in wafer thickness'20016,300,219'Method of forming trench isolation regions'20016,294,452'Controllable ovonic phase-change semiconductor memory device and methods of fabricating the same'20016,291,340'Method of forming low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer'20016,291,289'Method of forming DRAM trench capacitor with metal layer over hemispherical grain polysilicon'20016,284,660'Method for improving CMP processing'20016,281,103'Method for fabricating gate semiconductor'20016,281,091'Container capacitor structure and method of formation thereof'20016,281,109'Advance metallization process'20016,274,423'Etch process for aligning a capacitor structure and an adjacent contact corridor'20016,271,561'Method for fabricating floating gate semiconductor devices with trench isolation structures and self aligned floating gates'20016,261,151'System for real-time control of semiconductor wafer polishing'20016,255,216'Methods of forming a contact having titanium silicide and titanium formed by chemical vapor deposition'20016,255,209'Methods of forming a contact having titanium formed by chemical vapor deposition'20016,254,928'Laser pyrolysis particle forming method and particle forming method'20016,235,571'Uniform dielectric layer and method to form same'20016,221,779'Self-aligned process for making contacts to silicon substrates during the manufacture of integrated circuits therein'20016,214,726'Method of producing rough polysilicon by the use of pulsed plasma chemical vapor deposition and products produced by same'20016,208,425'Endpoint detector and method for measuring a change in wafer thickness in chemical-mechanical polishing of semiconductor wafers'20016,208,033'Apparatus having titanium silicide and titanium formed by chemical vapor deposition'20016,207,571'Self-aligned contact formation for semiconductor devices'2001RE037104'Planarization of a gate electrode for improved gate patterning over non-planar active area isolation'20016,200,842'Method of forming complementary type conductive regions on a substrate'20016,194,746'Vertical diode structures with low series resistance'20016,184,127'Semiconductor processing method of forming a contact opening to a region adjacent a field isolation mass, and a semiconductor structure'20016,174,821'Semiconductor processing method of depositing polysilicon'20016,171,943'Methods of forming a contact having titanium silicide formed by chemical vapor deposition'20016,159,818'Method of forming a container capacitor structure'2000

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1990–2012Based in Boise, ID, US· patent location history
1991–2013Patents assigned to MICRON TECHNOLOGY INC (351)· patent assignee history
2005–2020Patents assigned to APPLIED MATERIALS INC (11)· patent assignee history
2005–2018Based in Los Gatos, CA, US· patent location history
2006–2013Based in Vallejo, CA, US· patent location history
2008–2015Based in Baoshan Township, TW· patent location history
2010–2016Patents assigned to SEMILEDS OPTOELECTRONICS CO (29)· patent assignee history
2011–2015Patents assigned to DOAN TRUNG TRI (17)· patent assignee history
2011–2015Patents assigned to CHU CHEN-FU (12)· patent assignee history
2011–2020Based in Hsinchu, TW· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MICRON TECHNOLOGY INC3511991–2013
SEMILEDS OPTOELECTRONICS CO292010–2016
DOAN TRUNG TRIself172011–2015
CHU CHEN-FU122011–2015
APPLIED MATERIALS INC112005–2020
Locations
LocationPatentsSpan
Boise, ID, US3501990–2012
Baoshan Township, TW252008–2015
Los Gatos, California, US222005–2018
Vallejo, California, US122006–2013
Hsinchu, TW82011–2020