Inventor
John Jianshi Wang
Inventor
San Jose, CA, US
Overview
Patents· 50 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices18%
H10DInorganic electric semiconductor devices15%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1013%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests9%
G11CStatic stores5%
H01GCapacitors5%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution5%
B82YSpecific uses or applications of nanostructures4%
G01RMeasuring electric variables3%
PatentTitleYear
10,889,497Sheet-shaped nitrogen-phosphorus co-doped porous carbon material and method for preparation thereof and use thereof202110,805,101Collaborative communications environment and automatic account creation thereof202010,741,337Mesoporous nanocrystalline film architecture for capacitive storage devices202010,056,199Mesoporous nanocrystalline film architecture for capacitive storage devices20189,721,310'Facet-based filtering of social network update data'20179,653,219'Mesoporous nanocrystalline film architecture for capacitive storage devices'20178,996,536'Facet-based filtering of social network update data'20158,850,451'Subscribing for application messages in a multicast messaging environment'20148,675,346'Mesoporous nanocrystalline film architecture for capacitive storage devices'20147,137,085'Wafer level global bitmap characterization in integrated circuit technology development'20067,101,722'In-line voltage contrast determination of tunnel oxide weakness in integrated circuit technology development'20067,099,789'Characterizing distribution signatures in integrated circuit technology'20067,020,022'Method of reference cell design for optimized memory circuit yield'20066,924,220'Self-aligned gate formation using polysilicon polish with peripheral protective layer'20056,825,083'Method for reducing shallow trench isolation edge thinning on thin gate oxides to improve peripheral transistor reliability and performance for high performance flash memory devices'20046,797,650'Flash memory devices with oxynitride dielectric as the charge storage media'20046,784,061'Process to improve the Vss line formation for high density flash memory and related structure associated therewith'20046,777,957'Test structure to measure interlayer dielectric effects and breakdown and detect metal defects in flash memories'20046,764,920'Method for reducing shallow trench isolation edge thinning on tunnel oxides using partial nitride strip and small bird\'s beak formation for high performance flash memory devices'20046,734,080'Semiconductor isolation material deposition system and method'20046,717,850'Efficient method to detect process induced defects in the gate stack of flash memory devices'20046,590,260'Memory device having improved programmability'20036,445,051'Method and system for providing contacts with greater tolerance for misalignment in a flash memory'20026,423,612'Method of fabricating a shallow trench isolation structure with reduced topography'20026,420,240'Method for reducing the step height of shallow trench isolation structures'20026,410,949'Flash memory device with monitor structure for monitoring second gate over-etch'20026,410,458'Method and system for eliminating voids in a semiconductor device'20026,380,029'Method of forming ono stacked films and DCS tungsten silicide gate to improve polycide gate performance for flash memory devices'20026,376,309'Method for reduced gate aspect ratio to improve gap-fill after spacer etch'20026,365,945'Submicron semiconductor device having a self-aligned channel stop region and a method for fabricating the semiconductor device using a trim and etch'20026,362,049'High yield performance semiconductor process flow for NAND flash memory products'20026,355,522'Effect of doped amorphous Si thickness on better poly 1 contact resistance performance for nand type flash memory devices'20026,350,627'Interlevel dielectric thickness monitor for complex semiconductor chips'20026,331,954'Determination of misalignment for floating gates near a gate stack bending point in array of flash memory cells'20016,323,047'Method for monitoring second gate over-etch in a semiconductor device'20016,312,991'Elimination of poly cap easy poly 1 contact for NAND product'20016,300,658'Method for reduced gate aspect ration to improve gap-fill after spacer etch'20016,281,078'Manufacturing process to eliminate ONO fence material in high density NAND-type flash memory devices'20016,211,058'Semiconductor device with multiple contact sizes'20016,180,454'Method for forming flash memory devices'20016,177,312'Method for removing contaminate nitrogen from the peripheral gate region of a non-volatile memory device during production of such device'20016,177,316'Post barrier metal contact implantation to minimize out diffusion for NAND device'20016,140,246'In-situ P doped amorphous silicon by NH3 to form oxidation resistant and finer grain floating gates'20006,072,191'Interlevel dielectric thickness monitor for complex semiconductor chips'20006,066,873'Method and apparatus for preventing P1 punchthrough'20006,063,668'Poly I spacer manufacturing process to eliminate polystringers in high density nand-type flash memory devices'20006,057,193'Elimination of poly cap for easy poly1 contact for NAND product'20006,017,786'Method for forming a low barrier height oxide layer on a silicon substrate'20005,994,780'Semiconductor device with multiple contact sizes'19995,972,749'Method for preventing P1 punchthrough'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2006Patents assigned to ADVANCED MICRO DEVICES INC (40)· patent assignee history
1999–2017Based in San Jose, CA, US· patent location history
2000–2001Patents assigned to FUJITSU LTD (3)· patent assignee history
2014–2020Patents assigned to UNIV CALIFORNIA (4)· patent assignee history
2014–2015Patents assigned to WANG JOHN (2)· patent assignee history
2014–2020Based in Glendora, CA, US· patent location history
2015–2017Patents assigned to LINKEDIN CORP (2)· patent assignee history
2015Based in Mountain View, CA, US· patent location history
2020Based in Belmont, CA, US· patent location history
2021Based in Zhejiang, CN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADVANCED MICRO DEVICES INC | 40 | 1999–2006 |
| UNIV CALIFORNIA | 4 | 2014–2020 |
| FUJITSU LTD | 3 | 2000–2001 |
| LINKEDIN CORP | 2 | 2015–2017 |
| WANG JOHNself | 2 | 2014–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 42 | 1999–2017 |
| Glendora, California, US | 4 | 2014–2020 |
| Zhejiang, CN | 1 | 2021 |
| Belmont, California, US | 1 | 2020 |
| Mountain View, California, US | 1 | 2015 |