Inventor
Trung Diep
Inventor
San Jose, CA, US
Overview
Patents· 20 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing69%
G11CStatic stores14%
H04LTransmission of digital information, e.g. telegraphic communication10%
G09CCiphering or deciphering apparatus for cryptographic or other purposes involving the need for secrecy3%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use3%
PatentTitleYear
10,853,261Methods and apparatuses for addressing memory caches202010,515,010Wear leveling in a memory system201910,133,676Cache memory that supports tagless addressing201810,102,140Methods and apparatuses for addressing memory caches201810,037,433Secure text retrieval20189,934,142Wear leveling in a memory system20189,734,357'Process authenticated memory page encryption'20179,569,359'Methods and apparatuses for addressing memory caches'20179,465,961'Methods and circuits for securing proprietary memory transactions'20169,442,838'Remapping memory cells based on future endurance measurements'20169,390,025'Wear leveling in a memory system'20169,262,342'Process authenticated memory page encryption'20169,069,605'Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention'20158,935,489'Adaptively time-multiplexing memory references from multiple processor cores'20158,887,174'Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers'20148,607,235'Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention'20138,205,200'Compiler-based scheduling optimization hints for user-level threads'20128,010,969'Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers'20117,810,083'Mechanism to emulate user-level multithreading on an OS-sequestered sequencer'20106,330,646'Arbitration mechanism for a computer system having a unified memory architecture'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2015Patents assigned to INTEL CORP (7)· patent assignee history
2001Based in Folsom, CA, US· patent location history
2010–2020Based in San Jose, CA, US· patent location history
2012–2014Patents assigned to HANKINS RICHARD A (3)· patent assignee history
2012–2014Patents assigned to WANG HONG (3)· patent assignee history
2013–2018Patents assigned to DIEP TRUNG A (4)· patent assignee history
2015–2020Patents assigned to RAMBUS INC (12)· patent assignee history
2018Based in Palo Alto, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| RAMBUS INC | 12 | 2015–2020 |
| INTEL CORP | 7 | 2001–2015 |
| DIEP TRUNG Aself | 4 | 2013–2018 |
| HANKINS RICHARD A | 3 | 2012–2014 |
| WANG HONG | 3 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 18 | 2010–2020 |
| Palo Alto, California, US | 1 | 2018 |
| Folsom, California, US | 1 | 2001 |