Inventor
Jayachandra B. Avula
Inventor
Austin, TX, US
Overview
Patents· 3 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing100%
PatentTitleYear
5,884,060'Processor which performs dynamic instruction scheduling at time of execution within a single clock cycle'19995,640,588'CPU architecture performing dynamic instruction scheduling at time of execution within single clock cycle'19975,488,729'Central processing unit architecture with symmetric instruction scheduling to achieve multiple instruction launch and execution'1996Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1996–1999Patents assigned to ROSS TECHNOLOGY INC (3)· patent assignee history
1996–1999Based in Austin, TX, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ROSS TECHNOLOGY INC | 3 | 1996–1999 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 3 | 1996–1999 |