Inventor
KYLE K. KIRBY
Inventor
US
Overview
Patents· 40 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices34%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1034%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
H10BElectronic memory devices6%
H10DInorganic electric semiconductor devices5%
G11CStatic stores4%
B24BMachines, devices, or processes for grinding or polishing1%
H01FMagnets1%
H05KPrinted circuits1%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution1%
PatentTitleYear
12,582,001Methods for fusion bonding semiconductor devices to temporary carrier wafers with cavity regions for reduced bond strength, and semiconductor device assemblies formed by the same202612,568,869Semiconductor device circuitry formed from remote reservoirs202612,469,809Semiconductor interconnect structures with vertically offset bonding surfaces, and associated systems and methods202512,451,455Systems and methods for direct bonding in semiconductor die manufacturing202512,424,516Monolithic conductive column in a semiconductor device and associated methods202512,424,517Monolithic conductive cylinder in a semiconductor device and associated methods202512,381,131Front end of line interconnect structures and associated systems and methods202512,368,096Microelectronic devices with through-substrate interconnects and associated methods of manufacturing202512,368,131Embedded nanoparticles for on-die thermal enhancement of hybrid bonding and associated systems and methods202512,334,448Front end of line interconnect structures and associated systems and methods202512,334,469Piezoelectric materials for on-die thermal enhancement of hybrid bonding and associated systems and methods202512,308,348Multi-height interconnect structures and associated systems and methods202512,300,570Grindable heat sink for multiple die packaging202512,191,162Semiconductor device assembly with pillar array202512,183,716Monolithic conductive columns in a semiconductor device and associated methods202412,107,050Front end of line interconnect structures and associated systems and methods202412,074,094Monolithic conductive column in a semiconductor device and associated methods202412,046,559Semiconductor memory stacks connected to processing units and associated systems and methods202411,978,656Semiconductor with through-substrate interconnect202411,973,062High density pillar interconnect conversion with stack to substrate connection202411,942,428Inductors with through-substrate via cores202411,942,444Semiconductor interconnect structures with vertically offset bonding surfaces, and associated systems and methods202411,862,569Front end of line interconnect structures and associated systems and methods202411,823,977Semiconductor devices with back-side coils for wireless signal and power coupling202311,817,305Front end of line interconnect structures and associated systems and methods202311,776,926Combination-bonded die pair packaging and associated systems and methods202311,769,738Apparatuses exhibiting enhanced stress resistance and planarity, and related microelectronic devices and memory devices202311,735,568Semiconductor die stacks and associated systems and methods202311,735,528Semiconductor memory stacks connected to processing units and associated systems and methods202311,631,644High density pillar interconnect conversion with stack to substrate connection202311,587,912High density pillar interconnect conversion with stack to substrate connection202311,587,895Semiconductor interconnect structures with vertically offset bonding surfaces, and associated systems and methods202311,569,203Multi-height interconnect structures and associated systems and methods202311,532,5783DI solder cup202211,527,436Microelectronic devices with through-substrate interconnects and associated methods of manufacturing202211,289,440Combination-bonded die pair packaging and associated systems and methods202211,239,207Semiconductor die stacks and associated systems and methods202211,239,169Semiconductor memory stacks connected to processing units and associated systems and methods202211,195,740Methods and apparatus for wafer handling and processing202111,177,175Microelectronic devices and methods for filling vias in microelectronic devices2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to MICRON TECHNOLOGY INC (39)· patent assignee history
2021–2026Based in US· patent location history
2025Patents assigned to LODESTAR LICENSING GROUP LLC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 39 | 2021–2026 |
| LODESTAR LICENSING GROUP LLC | 1 | 2025 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 40 | 2021–2026 |