Inventor
Robert McKenzie
Inventor
Ottawa, CA
Overview
Patents· 25 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores53%
G06FElectric digital data processing24%
H04LTransmission of digital information, e.g. telegraphic communication7%
H03KPulse technique4%
H03FAmplifiers2%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses2%
H03MCoding2%
H04BTransmission2%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%
PatentTitleYear
11,037,625Solid state drive architectures202110,796,762Solid state drive architectures202010,790,790Amplifiers with delta-sigma modulators using pulse-density modulations and related processes2020RE046819Synchronous memory read data capture20189,941,007Solid state drive architectures2018RE043552'Block programmable priority encoder in a cam'20128,086,813'Synchronous memory read data capture'20117,889,580'Memory system having incorrupted strobe signals'20117,685,393'Synchronous memory read data capture'20107,652,932'Memory system having incorrupted strobe signals'20107,558,909'Method and apparatus for wide word deletion in content addressable memories'20097,502,245'Content addressable memory architecture'20097,478,193'Method and apparatus for interconnecting content addressable memory devices'20097,382,638'Matchline sense circuit and method'20087,353,330'Method and apparatus for performing repeated content addressable memory searches'20087,334,093'Block programmable priority encoder in a CAM'20087,251,148'Matchline sense circuit and method'20077,188,211'Block programmable priority encoder in a CAM'20077,136,961'Method and apparatus for wide word deletion in content addressable memories'20067,062,601'Method and apparatus for interconnecting content addressable memory devices'20067,043,601'Priority encoder circuit and method'20067,002,824'Content addressable memory architecture'20066,987,682'Matchline sense circuit and method'20066,775,166'Content addressable memory architecture'20046,693,814'Priority encoder circuit and method'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2012Patents assigned to MOSAID TECHNOLOGIES INC (19)· patent assignee history
2004–2018Based in Ottawa, CA· patent location history
2011–2012Patents assigned to MCKENZIE ROBERT (2)· patent assignee history
2011Patents assigned to GILLINGHAM PETER (1)· patent assignee history
2012–2021Based in Toronto, CA· patent location history
2018–2021Patents assigned to THSTYME BERMUDA LTD (3)· patent assignee history
2018Patents assigned to CONVERSANT INTELLECTUAL PROPERTY MAN INC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MOSAID TECHNOLOGIES INC | 19 | 2004–2012 |
| THSTYME BERMUDA LTD | 3 | 2018–2021 |
| MCKENZIE ROBERTself | 2 | 2011–2012 |
| CONVERSANT INTELLECTUAL PROPERTY MAN INC | 1 | 2018 |
| GILLINGHAM PETER | 1 | 2011 |
Locations
| Location | Patents | Span |
|---|---|---|
| Ottawa, CA | 20 | 2004–2018 |
| Toronto, CA | 5 | 2012–2021 |