Inventor

Amit A. Merchant

Inventor

Portland, OR, US

Overview

1993–2021

Patent span

Physics

Primary field (CPC G)

Patents· 39 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing77%

G11CStatic stores11%

H04LTransmission of digital information, e.g. telegraphic communication7%

G11BInformation storage based on relative movement between record carrier and transducer2%

H04MTelephonic communication2%

PatentTitleYear

11,113,242Programmatically choosing preferred storage parameters for files in large-scale distributed storage systems2021 RE048550Use of abstracted data in pattern matching system2021 9,178,939'Auto incorporation of new components into a hierarchical network'2015 9,178,770'Auto incorporation of new components into a hierarchical network'2015 8,898,434'Optimizing system throughput by automatically altering thread co-execution based on operating system directives'2014 8,898,435'Optimizing system throughput by automatically altering thread co-execution based on operating system directives'2014 7,366,879'Alteration of functional unit partitioning scheme in multithreaded processor based upon thread statuses'2008 7,353,370'Method and apparatus for processing an event occurrence within a multithreaded processor'2008 7,219,349'Multi-threading techniques for a processor utilizing a replay queue'2007 7,200,737'Processor with a replay system that includes a replay queue for improved throughput'2007 7,089,409'Interface to a memory system for a processor having a replay system'2006 7,039,794'Method and apparatus for processing an event occurrence for a least one thread within a multithreaded processor'2006 6,889,319'Method and apparatus for entering and exiting multiple threads within a multithreaded processor'2005 6,792,446'Storing of instructions relating to a stalled thread'2004 6,785,803'Processor including replay queue to break livelocks'2004 6,772,322'Method and apparatus to monitor the performance of a processor'2004 6,665,792'Interface to a memory system for a processor having a replay system'2003 6,496,925'Method and apparatus for processing an event occurrence within a multithreaded processor'2002 6,385,715'Multi-threading for a processor utilizing a replay queue'2002 6,334,182'Scheduling operations using a dependency matrix'2001 6,212,626'Computer processor having a checker'2001 6,163,838'Computer processor with a replay system'2000 6,094,717'Computer processor with a replay system having a plurality of checkers'2000 5,909,699'Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency'1999 5,893,151'Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests'1999 5,890,200'Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests'1999 5,875,467'Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests'1999 5,797,026'Method and apparatus for self-snooping a bus during a boundary transaction'1998 5,778,438'Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests'1998 5,737,758'Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests'1998 5,737,759'Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests'1998 5,682,516'Computer system that maintains system wide cache coherency during deferred communication transactions'1997 5,572,703'Method and apparatus for snoop stretching using signals that convey snoop results'1996 5,572,702'Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency'1996 5,537,357'Method for preconditioning a nonvolatile memory array'1996 5,377,147'Method and circuitry for preconditioning shorted rows in a nonvolatile semiconductor memory incorporating row redundancy'1994 5,347,489'Method and circuitry for preconditioning shorted rows in a nonvolatile semiconductor memory incorporating row redundancy'1994 5,327,383'Method and circuitry for erasing a nonvolatile semiconductor memory incorporating row redundancy'1994 5,237,535'Method of repairing overerased cells in a flash memory'1993

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1993–2008Patents assigned to INTEL CORP (33)· patent assignee history

1993–1999Based in Citrus Heights, CA, US· patent location history

1996–2008Based in Portland, OR, US· patent location history

2014–2015Patents assigned to IBM (3)· patent assignee history

2014Patents assigned to LENOVO ENTPR SOLUTIONS SINGAPORE PTE LTD (2)· patent assignee history

2014–2015Based in Bangalore, IN· patent location history

2021Patents assigned to AFINITI INT HOLDINGS LTD (1)· patent assignee history

2021Patents assigned to AFINITI LTD (1)· patent assignee history

2021Based in Mountain View, CA, US· patent location history

2021Based in Bethesda, MD, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	33	1993–2008
IBM	3	2014–2015
LENOVO ENTPR SOLUTIONS SINGAPORE PTE LTD	2	2014
AFINITI INT HOLDINGS LTD	1	2021
AFINITI LTD	1	2021

Locations

Location	Patents	Span
Portland, OR, US	27	1996–2008
Citrus Heights, California, US	6	1993–1999
Bangalore, IN	4	2014–2015
Mountain View, California, US	1	2021
Bethesda, Maryland, US	1	2021