Inventor
Daniel H. Morris
Inventor
Hillsboro, OR, US
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores20%
H01LSemiconductor devices20%
H10BElectronic memory devices18%
H10DInorganic electric semiconductor devices15%
H03KPulse technique13%
G06FElectric digital data processing5%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%
E04FFinishing work on buildings, e.g. stairs, floors2%
H03MCoding2%
H10NElectric solid-state devices not otherwise provided for2%
PatentTitleYear
11,093,322Memory error recovery using shared structural element error correlations202110,975,575Construction panel mounting apparatus202110,832,761Polarization gate stack SRAM202010,777,250Save-restore circuitry with metal-ferroelectric-metal devices202010,749,104Combinatorial magneto electric spin orbit logic202010,748,602Nonvolatile SRAM202010,734,378Transistor threshold voltage variation optimization202010,720,504Transistor with dynamic threshold voltage for low-leakage standby and high speed active mode202010,720,438Memory array with ferroelectric elements202010,707,846Tunnel field-effect transistor (TFET) based high-density and low-power sequential202010,651,182Three-dimensional ferroelectric NOR-type memory202010,573,385Ferroelectric based memory cell with non-volatile retention202010,559,349Polarization gate stack SRAM202010,553,694Transistors with temperature compensating gate structures202010,355,005Semi-volatile embedded memory with between-fin floating-gate device and method201910,261,923Configurable interconnect apparatus and method20199,997,227Non-volatile ferroelectric logic with granular power-gating20189,985,611Tunnel field-effect transistor (TFET) based high-density and low-power sequential20189,842,643'Apparatuses, methods, and systems for dense circuitry using tunnel field effect transistors'20179,490,780'Apparatuses, methods, and systems for dense circuitry using tunnel field effect transistors'20169,117,523'Chainlink memory'20158,198,655'Regular pattern arrays for memory and logic on a semiconductor substrate'2012Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2012–2015Patents assigned to PILEGGI LAWRENCE T (2)· patent assignee history
2012–2015Based in Pittsburgh, PA, US· patent location history
2015Patents assigned to BROMBERG DAVID M (1)· patent assignee history
2016–2020Patents assigned to INTEL CORP (18)· patent assignee history
2016–2020Based in Hillsboro, OR, US· patent location history
2020Based in San Francisco, CA, US· patent location history
2021Patents assigned to ARTINYAN ARMEN (1)· patent assignee history
2021Patents assigned to FACEBOOK INC (1)· patent assignee history
2021Based in Palo Alto, CA, US· patent location history
2021Based in West Hills, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 18 | 2016–2020 |
| PILEGGI LAWRENCE T | 2 | 2012–2015 |
| ARTINYAN ARMEN | 1 | 2021 |
| BROMBERG DAVID M | 1 | 2015 |
| FACEBOOK INC | 1 | 2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hillsboro, OR, US | 17 | 2016–2020 |
| Pittsburgh, Pennsylvania, US | 2 | 2012–2015 |
| Palo Alto, California, US | 1 | 2021 |
| West Hills, California, US | 1 | 2021 |
| San Francisco, California, US | 1 | 2020 |