Inventor
Uwe Griebenow
Inventor
Markkleeberg, DE
Overview
Patents· 45 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices47%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%
H01LSemiconductor devices5%
G02BOptical elements, systems or apparatus2%
G06FElectric digital data processing2%
G11CStatic stores2%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation2%
H10NElectric solid-state devices not otherwise provided for2%
G01NInvestigating or analysing materials by determining their chemical or physical properties1%
PatentTitleYear
9,490,189'Semiconductor device comprising a stacked die configuration including an integrated peltier element'20169,184,095'Contact bars with reduced fringing capacitance in a semiconductor device'20159,054,207'Field effect transistors for a flash memory comprising a self-aligned charge storage region'20158,883,582'High-K gate electrode structure formed after transistor fabrication by using a spacer'20148,786,027'Transistors comprising high-K metal gate electrode structures and embedded strain-inducing semiconductor alloys formed in a late stage'20148,759,960'Semiconductor device comprising a stacked die configuration including an integrated Peltier element'20148,748,281'Enhanced confinement of sensitive materials of a high-K metal gate electrode structure'20148,735,237'Method for increasing penetration depth of drain and source implantation species for a given gate height'20148,673,713'Method for forming a transistor with recessed drain and source areas and non-conformal metal silicide regions'20148,669,151'High-K metal gate electrode structures formed at different process stages of a semiconductor device'20148,615,145'Semiconductor device comprising a buried waveguide for device internal optical communication'20138,574,991'Asymmetric transistor devices formed by asymmetric spacers and tilted implantation'20138,541,885'Technique for enhancing transistor performance by transistor specific contact design'20138,536,036'Predoped semiconductor material for a high-K metal gate electrode structure of P- and N-channel transistors'20138,508,008'Optical signal transfer in a semiconductor device by using monolithic opto-electronic components'20138,507,348'Field effect transistors for a flash memory comprising a self-aligned charge storage region'20138,470,661'High-K gate electrode structure formed after transistor fabrication by using a spacer'20138,455,314'Transistors comprising high-K metal gate electrode structures and embedded strain-inducing semiconductor alloys formed in a late stage'20138,450,163'Semiconductor device comprising metal gates and semiconductor resistors formed on the basis of a replacement gate approach'20138,440,534'Threshold adjustment for MOS devices by adapting a spacer width prior to implantation'20138,426,262'Stress adjustment in stressed dielectric materials of semiconductor devices by stress relaxation based on radiation'20138,426,266'Stress memorization with reduced fringing capacitance based on silicon nitride in MOS semiconductor devices'20138,409,942'Replacement gate approach based on a reverse offset spacer applied prior to work function metal deposition'20138,361,844'Method for adjusting the height of a gate electrode in a semiconductor device'20138,349,744'Double deposition of a stress-inducing layer in an interlayer dielectric with intermediate stress relaxation in a semiconductor device'20138,338,894'Increased depth of drain and source regions in complementary transistors by forming a deep drain and source region prior to a cavity etch'20128,329,531'Strain memorization in strained SOI substrates of semiconductor devices'20128,324,039'Reduced silicon thickness of N-channel transistors in SOI CMOS devices'20128,318,564'Performance enhancement in transistors comprising high-k metal gate stack by an early extension implantation'20128,278,174'In situ formed drain and source regions including a strain-inducing alloy and a graded dopant profile'20128,247,275'Strain engineering in three-dimensional transistors based on globally strained semiconductor base layers'20128,241,973'Method for increasing penetration depth of drain and source implantation species for a given gate height'20128,198,633'Stress transfer enhancement in transistors by a late gate re-crystallization'20128,198,152'Transistors comprising high-k metal gate electrode structures and adapted channel semiconductor materials'20128,158,482'Asymmetric transistor devices formed by asymmetric spacers and tilted implantation'20128,110,487'Method of creating a strained channel region in a transistor by deep implantation of strain-inducing species below the channel region'20128,105,962'Method and a semiconductor device comprising a protection layer for reducing stress relaxation in a dual stress liner approach'20128,039,342'Enhanced integrity of a high-K metal gate electrode structure by using a sacrificial spacer for cap removal'20118,034,669'Drive current adjustment for transistors formed in the same active region by locally providing embedded strain-inducing semiconductor material in the active region'20118,026,134'Recessed drain and source areas in combination with advanced silicide formation in transistors'20118,017,504'Transistor having a high-k metal gate stack and a compressively stressed channel'20117,964,970'Technique for enhancing transistor performance by transistor specific contact design'20117,887,978'Method of detecting repeating defects in lithography masks on the basis of test substrates exposed under varying conditions'20117,871,877'Technique for strain engineering in silicon-based transistors by using implantation techniques for forming a strain-inducing layer under the channel region'20117,855,118'Drive current increase in transistors by asymmetric amorphization implantation'2010Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2010–2014Patents assigned to ADVANCED MICRO DEVICES INC (13)· patent assignee history
2010–2016Based in Markkleeberg, DE· patent location history
2011–2016Patents assigned to GLOBALFOUNDRIES INC (32)· patent assignee history
2012–2015Patents assigned to GRIEBENOW UWE (33)· patent assignee history
2012–2015Patents assigned to HOENTSCHEL JAN (24)· patent assignee history
2012–2015Patents assigned to BEYER SVEN (15)· patent assignee history
2012–2015Based in Markleeberg, DE· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| GRIEBENOW UWEself | 33 | 2012–2015 |
| GLOBALFOUNDRIES INC | 32 | 2011–2016 |
| HOENTSCHEL JAN | 24 | 2012–2015 |
| BEYER SVEN | 15 | 2012–2015 |
| ADVANCED MICRO DEVICES INC | 13 | 2010–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Markkleeberg, DE | 37 | 2010–2016 |
| Markleeberg, DE | 8 | 2012–2015 |