Inventor

TONY M. BREWER

Inventor

US

Overview

2021–2026

Patent span

Physics

Primary field (CPC G)

Patents· 107 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing58%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use13%

G11CStatic stores7%

H01LSemiconductor devices4%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%

H10DInorganic electric semiconductor devices4%

H04LTransmission of digital information, e.g. telegraphic communication2%

H03KPulse technique2%

H10BElectronic memory devices2%

G01SRadio direction-finding1%

PatentTitleYear

12,591,470Mechanism to provide reliable receipt of event messages2026 12,554,648Evicting a cache line with pending control request2026 12,530,300Memory side cache request handling2026 12,530,149Method of submitting work to fabric attached memory2026 12,481,465Host-preferred memory operation2025 12,450,109Queueing asynchronous events for acceptance by threads executing in a barrel processor2025 12,436,714Access request reordering for memory-based communication queues2025 12,436,712Access request reordering across a multiple-channel interface for memory-based communication queues2025 12,437,800Row clear features for memory devices and associated methods and systems2025 12,430,264Selective cache line memory encryption2025 12,386,656Dynamic decomposition and thread allocation2025 12,367,148Variable execution time atomic operations2025 12,360,773Thread commencement using a work descriptor packet in a self-scheduling processor2025 12,321,274Recall pending cache line eviction2025 12,293,187Efficient processing of nested loops for computing device with multiple configurable processing elements using multiple spoke counts2025 12,277,065Shared virtual address spaces2025 12,266,6473D stacked integrated circuits having functional blocks configured to provide redundancy sites2025 12,242,385Virtual addresses for a memory system2025 12,222,893Connectivity in coarse grained reconfigurable architecture2025 12,204,363System having a hybrid threading processor, a hybrid threading fabric having configurable computing elements, and a hybrid interconnection network2025 12,197,351Methods and systems for requesting atomic operations in a computing system2025 12,182,048Multi-threaded, self-scheduling reconfigurable computing fabric2024 12,182,635Chained resource locking2024 12,182,622Thread priority management in a multi-threaded, self-scheduling processor2024 12,174,759Interpolation acceleration in a processor memory interface2024 12,164,464Multi-threaded, self-scheduling processor2024 12,118,224Fine grained resource management for rollback memory operations2024 12,118,230Method for providing logging for persistent memory2024 12,111,770Silent cache line eviction2024 12,111,758Synchronized request handling at a memory device2024 12,106,142System call management in a user-mode, multi-threaded, self-scheduling processor2024 12,106,099Execution or write mask generation for data selection in a multi-threaded, self-scheduling reconfigurable computing fabric2024 12,079,516Host-preferred memory operation2024 12,074,5993D stacked integrated circuits having failure management2024 12,067,418Thread creation on local or remote compute elements by a multi-threaded, self-scheduling processor2024 12,039,201Control parameter address virtualization2024 12,019,920Memory controller with programmable atomic operations2024 12,013,788Evicting a cache line with pending control request2024 12,008,243Reducing index update messages for memory-based communication queues2024 11,966,741Adjustment of load access size by a multi-threaded, self-scheduling processor to manage network congestion2024 11,960,768Memory-side cache directory-based request queue2024 11,960,403Variable execution time atomic operations2024 11,940,919Recall pending cache line eviction2024 11,935,869Power and temperature management for functional blocks implemented by a 3D stacked integrated circuit2024 11,928,025Memory device protection2024 11,915,057Computational partition for a multi-threaded, self-scheduling reconfigurable computing fabric2024 11,914,516Memory side cache request handling2024 11,899,953Method of efficiently identifying rollback requests2024 11,886,728Undo capability for memory devices2024 11,880,687System having a hybrid threading processor, a hybrid threading fabric having configurable computing elements, and a hybrid interconnection network2024 11,881,251Row clear features for memory devices and associated methods and systems2024 11,868,163Efficient loop execution for a multi-threaded, self-scheduling reconfigurable computing fabric2024 11,861,366Efficient processing of nested loops for computing device with multiple configurable processing elements using multiple spoke counts2024 11,841,823Connectivity in coarse grained reconfigurable architecture2023 11,836,524Memory interface for a multi-threaded, self-scheduling reconfigurable computing fabric2023 11,809,800Interface for data communication between chiplets or other integrated circuits on an interposer2023 11,809,872Thread commencement using a work descriptor packet in a self-scheduling processor2023 11,809,369Event messaging in a system having a self-scheduling processor and a hybrid threading fabric2023 11,809,343Transporting request types with different latencies2023 11,809,368Multi-threaded, self-scheduling processor2023 11,802,957Increasing cache hits for synthetic aperture radar2023 11,789,642Loading data from memory during dispatch2023 11,789,790Mechanism to trigger early termination of cooperating processes2023 11,782,710Execution or write mask generation for data selection in a multi-threaded, self-scheduling reconfigurable computing fabric2023 11,768,626Stencil data access from tile memory2023 11,764,212Functional blocks implemented by integrated circuit2023 11,762,661Counter for preventing completion of a thread including a non-blocking external device call with no-return indication2023 11,740,800Alleviating memory hotspots on systems with multiple memory controllers2023 11,726,914Bias control for a memory device2023 11,720,475Debugging dataflow computer architectures2023 11,714,704Modified checksum using a poison data pattern2023 11,688,7343D stacked integrated circuits having functional blocks configured to accelerate artificial neural network (ANN) computation2023 11,675,598Loop execution control for a multi-threaded, self-scheduling reconfigurable computing fabric using a reenter queue2023 11,675,734Loop thread order execution control of a multi-threaded, self-scheduling reconfigurable computing fabric2023 11,675,588Tile-based result buffering in memory-compute systems2023 11,675,713Avoiding deadlock with a fabric having multiple systems on chip2023 11,669,486Initialization sequencing of chiplet I/O channels within a chiplet system2023 11,636,034Write-back cache policy to limit data transfer time to a memory device2023 11,635,959Execution control of a multi-threaded, self-scheduling reconfigurable computing fabric2023 11,604,605Memory controller2023 11,586,571Multi-threaded, self-scheduling reconfigurable computing fabric2023 11,579,888Non-cached loads and stores in a system having a multi-threaded, self-scheduling processor2023 11,579,887System having a hybrid threading processor, a hybrid threading fabric having configurable computing elements, and a hybrid interconnection network2023 11,573,796Conditional branching control for a multi-threaded, self-scheduling reconfigurable computing fabric2023 11,573,834Computational partition for a multi-threaded, self-scheduling reconfigurable computing fabric2023 11,567,766Control registers to store thread identifiers for threaded loop execution in a self-scheduling reconfigurable computing fabric2023 11,550,642Mechanism to trigger early termination of cooperating processes2023 11,550,719Multiple data channel memory module architecture2023 11,531,543Backpressure control using a stop signal for a multi-threaded, self-scheduling reconfigurable computing fabric2022 11,513,839Memory request size management in a multi-threaded, self-scheduling processor2022 11,513,840Thread creation on local or remote compute elements by a multi-threaded, self-scheduling processor2022 11,513,837Thread commencement and completion using work descriptor packets in a system having a self-scheduling processor and a hybrid threading fabric2022 11,513,838Thread state monitoring in a system having a multi-threaded, self-scheduling processor2022 11,507,493Debugging dataflow computer architectures2022 11,488,9453D stacked integrated circuits having functional blocks configured to provide redundancy sites2022 11,481,343Transporting request types with different latencies2022 11,461,527Interface for data communication between chiplets or other integrated circuits on an interposer2022 11,461,048Memory controller with programmable atomic operations2022 11,442,858Bias control for a memory device2022 11,430,504Row clear features for memory devices and associated methods and systems2022 11,416,331Modified checksum using a poison data pattern2022 11,409,601Memory device protection2022 11,288,074Loop execution control for a multi-threaded, self-scheduling reconfigurable computing fabric using a reenter queue2022 11,275,710Loop thread order execution control of a multi-threaded, self-scheduling reconfigurable computing fabric2022 11,249,907Write-back cache policy to limit data transfer time to a memory device2022 11,157,286Non-cached loads and stores in a system having a multi-threaded, self-scheduling processor2021 11,150,900Execution or write mask generation for data selection in a multi-threaded, self-scheduling reconfigurable computing fabric2021

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2021–2026Patents assigned to MICRON TECHNOLOGY INC (105)· patent assignee history

2021–2026Based in US· patent location history

2024–2025Patents assigned to LODESTAR LICENSING GROUP LLC (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MICRON TECHNOLOGY INC	105	2021–2026
LODESTAR LICENSING GROUP LLC	2	2024–2025

Locations

Location	Patents	Span
US	107	2021–2026