Inventor
Shivnandan D. Kaushik
Inventor
Portland, OR, US
Overview
Patents· 46 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing88%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use12%
PatentTitleYear
10,452,403Mechanism for instruction set based thread execution on a plurality of instruction sequencers20199,990,206Mechanism for instruction set based thread execution of a plurality of instruction sequencers20189,875,102Apparatus, system, and method for persistent user-level thread20189,766,891'Apparatus, system, and method for persistent user-level thread'20179,720,697'Mechanism for instruction set based thread execution on a plurality of instruction sequencers'20179,383,997'Apparatus, system, and method for persistent user-level thread'20169,069,605'Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention'20159,043,521'Technique for communicating interrupts in a computer system'20158,984,199'Inter-processor interrupts'20158,887,174'Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers'20148,719,819'Mechanism for instruction set based thread execution on a plurality of instruction sequencers'20148,607,235'Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention'20138,516,483'Transparent support for operating system services for a sequestered sequencer'20138,479,217'Apparatus, system, and method for persistent user-level thread'20138,332,619'Primitives to enhance thread-level speculation'20128,312,198'Technique for communicating interrupts in a computer system'20128,171,268'Technique for context state management to reduce save and restore operations between a memory and a processor using in-use vectors'20128,032,681'Processor selection for an interrupt based on willingness to accept the interrupt and on priority'20118,028,295'Apparatus, system, and method for persistent user-level thread'20118,010,969'Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers'20117,979,699'Processing capacity on demand'20117,882,339'Primitives to enhance thread-level speculation'20117,822,900'Apparatus and method for enumeration of processors during hot-plug of a compute node'20107,769,938'Processor selection for an interrupt identifying a processor cluster'20107,761,720'Mechanism for processor power state aware distribution of lowest priority interrupts'20107,743,233'Sequencer address management'20107,673,090'Hot plug interface control method and apparatus'20107,640,384'Queued locks using monitor-memory wait'20097,627,706'Creation of logical APIC ID with cluster ID and intra-cluster ID'20097,546,487'OS and firmware coordinated error handling using transparent firmware intercept and firmware services'20097,493,438'Apparatus and method for enumeration of processors during hot-plug of a compute node'20097,376,775'Apparatus, system, and method to enable transparent memory hot plug/remove'20087,360,103'P-state feedback to operating system with hardware coordination'20087,328,293'Queued locks using monitor-memory wait'20087,315,952'Power state coordination between devices sharing power-managed resources'20087,272,741'Hardware coordination of power management activities'20077,213,093'Queued locks using monitor-memory wait'20077,191,349'Mechanism for processor power state aware distribution of lowest priority interrupt'20077,146,514'Determining target operating frequencies for a multiprocessor system'20067,117,396'Scalable CPU error recorder'20067,117,311'Hot plug cache coherent interface method and apparatus'20067,000,102'Platform and method for supporting hibernate operations'20066,920,581'Method and apparatus for functional redundancy check mode recovery'20056,917,999'Platform and method for initializing components within hot-plugged nodes'20056,857,066'Apparatus and method to identify the maximum operating frequency of a processor'20056,526,431'Maintaining extended and traditional states of a processing unit in task switching'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2019Patents assigned to INTEL CORP (46)· patent assignee history
2003–2019Based in Portland, OR, US· patent location history
2012–2017Patents assigned to KAUSHIK SHIVNANDAN D (8)· patent assignee history
2012–2017Patents assigned to WANG HONG (8)· patent assignee history
2013–2017Patents assigned to PATEL BAIJU V (6)· patent assignee history
2013–2017Patents assigned to SETHI PRASHANT (6)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 46 | 2003–2019 |
| KAUSHIK SHIVNANDAN Dself | 8 | 2012–2017 |
| WANG HONG | 8 | 2012–2017 |
| PATEL BAIJU V | 6 | 2013–2017 |
| SETHI PRASHANT | 6 | 2013–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Portland, OR, US | 46 | 2003–2019 |