Inventor
Yervant Zorian
Inventor
Santa Clara, CA, US
Overview
Patents· 43 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores52%
G01RMeasuring electric variables19%
G06FElectric digital data processing19%
H01LSemiconductor devices3%
H10BElectronic memory devices3%
H10DInorganic electric semiconductor devices3%
PatentTitleYear
11,023,310Detection of address errors in memory devices using multi-segment error detection codes202110,789,398Method and apparatus for SOC with optimal RSMA202010,192,635FinFET-based memory testing using multiple read operations201910,115,477FinFET-based memory testing using multiple read operations20189,831,000Testing electronic memories based on fault and test algorithm periodicity20179,541,591'Periodic signal measurement using statistical sampling'20179,514,258'Generation of memory structural model based on memory layout'20169,336,342'Memory hard macro partition optimization for testing embedded memories'20169,053,050'Determining a desirable number of segments for a multi-segment single error correcting coding scheme'20158,850,277'Detecting random telegraph noise induced failures in an electronic memory'20148,359,553'Various methods and apparatuses for effective yield enhancement of good chip dies having memories per wafer'20138,295,108'Architecture, system and method for compressing repair data in an integrated circuit (IC) design'20128,225,156'Methods and apparatuses for external voltage test methodology of input-output circuits'20128,112,730'Various methods and apparatuses for memory modeling using a structural primitive verification for memory compilers'20127,898,882'Architecture, system and method for compressing repair data in an integrated circuit (IC) design'20117,890,900'Various methods and apparatuses for effective yield enhancement of good chip dies having memories per wafer'20117,856,581'Methods and apparatuses for external test methodology and initialization of input-output circuits'20107,853,847'Methods and apparatuses for external voltage test of input-output circuits'20107,788,551'System and method for repairing a memory'20107,768,840'Memory modeling using an intermediate level structural description'20107,673,264'System and method for verifying IP integrity in system-on-chip (SOC) design'20107,590,902'Methods and apparatuses for external delay test of input-output circuits'20097,519,888'Input-output device testing'20097,415,640'Methods and apparatuses that reduce the size of a repair data container for repairable memories'20087,415,641'System and method for repairing a memory'20087,290,186'Method and apparatus for a command based bist for testing memories'20077,237,154'Apparatus and method to generate a repair signature'20077,149,924'Apparatus, method, and system having a pin to activate the self-test and repair instructions'20067,149,921'Apparatus, method, and system to allocate redundant components with subsets of the redundant components'20067,127,647'Apparatus, method, and system to allocate redundant components'20066,397,349'Built-in self-test and self-repair methods and devices for computer memories comprising a reconfiguration memory device'20026,330,696'Self-testing of DRAMs for multiple faults'20016,317,846'System and method for detecting faults in computer memories using a look up table'20016,237,123'Built-in self-test controlled by a token network and method'20016,205,564'Optimized built-in self-test method and apparatus for random access memories'20015,978,935'Method for built-in self-testing of ring-address FIFOs having a data input register with transparent latches'19995,978,947'Built-in self-test in a plurality of stages controlled by a token passing network and method'19995,960,009'Built in shelf test method and apparatus for booth multipliers'19995,570,374'Built-in self-test control network'19965,513,318'Method for built-in self-testing of ring-address FIFOs'19965,381,419'Method and apparatus for detecting retention faults in memories'19955,107,501'Built-in self-test technique for content-addressable memories'19925,091,908'Built-in self-test technique for read-only memories'1992Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1992–2001Based in Princeton, NJ, US· patent location history
1996–2001Patents assigned to LUCENT TECHNOLOGIES INC (6)· patent assignee history
1999–2017Based in Santa Clara, CA, US· patent location history
2001Based in Somerset, NJ, US· patent location history
2006–2010Patents assigned to VIRAGE LOGIC CORP (12)· patent assignee history
2010–2021Patents assigned to SYNOPSYS INC (18)· patent assignee history
2012–2016Patents assigned to ZORIAN YERVANT (8)· patent assignee history
2012–2016Patents assigned to VARDANIAN VALERY (5)· patent assignee history
2018–2021Based in Mountain View, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SYNOPSYS INC | 18 | 2010–2021 |
| VIRAGE LOGIC CORP | 12 | 2006–2010 |
| ZORIAN YERVANTself | 8 | 2012–2016 |
| LUCENT TECHNOLOGIES INC | 6 | 1996–2001 |
| VARDANIAN VALERY | 5 | 2012–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Santa Clara, California, US | 31 | 1999–2017 |
| Princeton, New Jersey, US | 7 | 1992–2001 |
| Mountain View, California, US | 4 | 2018–2021 |
| Somerset, New Jersey, US | 1 | 2001 |