Inventor
Jamshed Jalal
Inventor
Austin, TX, US
Overview
Patents· 44 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing81%
H04LTransmission of digital information, e.g. telegraphic communication13%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use6%
PatentTitleYear
11,119,961I/O coherent request node for data processing network with improved handling of write operations202111,086,802Apparatus and method for routing access requests in an interconnect202111,074,206Message protocol for a data processing system202111,055,250Non-forwardable transfers202110,970,225Apparatus and method for handling cache maintenance operations202110,942,865Snooping with access permissions202110,917,198Transfer protocol in a data processing network202110,877,904System, method and apparatus for accessing shared memory202010,877,836Method and apparatus for coherent interconnect recovery with protocol layer re-transmission202010,853,271System architecture with query based address translation for access validation202010,795,820Read transaction tracker lifetimes in a coherent interconnect system202010,783,080Cache maintenance operations in a data processing system202010,761,987Apparatus and method for processing an ownership upgrade request for cached data that is issued in relation to a conditional store operation202010,725,958System, method and apparatus for enabling partial data transfers with indicators202010,713,187Memory controller having data access hint message for specifying the given range of one or more memory addresses202010,698,825Inter-chip communication in a multi-chip system202010,657,055Apparatus and method for managing snoop operations202010,628,355Apparatus and method for processing burst read transactions202010,613,996Separating completion and data responses for higher read throughput and lower link utilization in a data processing network202010,579,526Responding to snoop requests202010,489,315Dynamic adaptation of direct memory transfer in a data processing system with mismatched data-bus widths201910,489,323Data processing system for a home node to authorize a master to bypass the home node to directly send data to a slave201910,452,593High-performance streaming of ordered write stashes to enable optimized data sharing between I/O masters and CPUs201910,452,575System, method and apparatus for ordering logic201910,423,466Optimized streaming in an un-ordered interconnect201910,402,349Memory controller having data access hint message for specifying the given range of one or more memory addresses201910,310,979Snoop filter for cache coherency in a data processing system201910,282,297Read-with overridable-invalidate transaction201910,185,663Cache bypass201910,157,133Snoop filter for cache coherency in a data processing system201810,042,766Data processing apparatus with snoop request address alignment and snoop response time alignment20189,990,292Progressive fine to coarse grain snoop filter20189,900,260'Efficient support for variable width data channels in an interconnect network'20189,639,470'Coherency checking of invalidate transactions caused by snoop filter eviction in an integrated circuit'20179,507,716'Coherency checking of invalidate transactions caused by snoop filter eviction in an integrated circuit'20169,477,600'Apparatus and method for shared cache control including cache lines selectively operable in inclusive or non-inclusive mode'20169,372,798'Data processing apparatus having first and second protocol domains, and method for the data processing apparatus'20168,949,547'Coherency controller and method for data hazard handling for copending data access requests'20158,935,485'Snoop filter and non-inclusive shared cache memory'20158,490,107'Processing resource allocation within an integrated circuit supporting transaction requests of different priority levels'20138,463,960'Synchronisation of data processing systems'20138,463,958'Dynamic resource allocation for transaction requests issued by initiator devices to recipient devices'20137,069,384'System and method for cache external writing and write shadowing'20066,842,822'System and method for cache external writing'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2006Based in Cedar Park, TX, US· patent location history
2013–2021Patents assigned to ADVANCED RISC MACH LTD (42)· patent assignee history
2013–2016Patents assigned to JALAL JAMSHED (7)· patent assignee history
2013–2016Patents assigned to FILIPPO MICHAEL ALAN (6)· patent assignee history
2013–2016Patents assigned to MANNAVA PHANINDRA KUMAR (5)· patent assignee history
2013–2016Patents assigned to PRASADH RAMAMOORTHY GURU (5)· patent assignee history
2013–2021Based in Austin, TX, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADVANCED RISC MACH LTD | 42 | 2013–2021 |
| JALAL JAMSHEDself | 7 | 2013–2016 |
| FILIPPO MICHAEL ALAN | 6 | 2013–2016 |
| MANNAVA PHANINDRA KUMAR | 5 | 2013–2016 |
| PRASADH RAMAMOORTHY GURU | 5 | 2013–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 42 | 2013–2021 |
| Cedar Park, Texas, US | 2 | 2005–2006 |