Inventor
Sunil Suresh Hatti
Inventor
Karnataka, IN
Overview
Patents· 15 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing78%
G01RMeasuring electric variables11%
G11CStatic stores11%
PatentTitleYear
8,127,192'Predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification/validation in interrupt mode'20128,099,559'System and method for generating fast instruction and data interrupts for processor design verification and validation'20128,019,566'System and method for efficiently testing cache congruence classes during processor design verification and validation'20118,006,221'System and method for testing multiple processor modes for processor design verification and validation'20117,992,059'System and method for testing a large memory area during processor design verification and validation'20117,966,521'Light weight and high throughput test case generation methodology for testing cache/TLB intervention and diagnostics'20117,797,650'System and method for testing SLB and TLB cells during processor design verification and validation'20107,752,499'System and method for using resource pools and instruction pools for processor design verification and validation'20107,747,908'System and method for creating different start cache and bus states using multiple test patterns for processor design verification and validation'20107,739,570'System and method for increasing error checking performance by calculating CRC calculations after multiple test patterns for processor design verification and validation'20107,689,886'System and method for predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification and validation'20107,669,083'System and method for re-shuffling test case instruction orders for processor design verification and validation'20107,661,023'System and method for verification of cache snoop logic and coherency between instruction & data caches for processor design verification and validation'20107,647,539'System and method of testing using test pattern re-execution in varying timing scenarios for processor design verification and validation'20107,584,394'System and method for pseudo-random test pattern memory allocation for processor design verification and validation'2009Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2009–2012Patents assigned to IBM (15)· patent assignee history
2009–2012Based in Karnataka, IN· patent location history
2010–2012Based in Gokul, IN· patent location history
2012Patents assigned to DUSANAPUDI MANOJ (2)· patent assignee history
2012Patents assigned to HATTI SUNIL SURESH (2)· patent assignee history
2012Patents assigned to KAPOOR SHAKTI (2)· patent assignee history
2012Patents assigned to ANVEKAR DIVYA S (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 15 | 2009–2012 |
| DUSANAPUDI MANOJ | 2 | 2012 |
| HATTI SUNIL SURESHself | 2 | 2012 |
| KAPOOR SHAKTI | 2 | 2012 |
| ANVEKAR DIVYA S | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Karnataka, IN | 12 | 2009–2012 |
| Gokul, IN | 3 | 2010–2012 |