Inventor

Iqbal R. Rajwani

Inventor

Roseville, CA, US

Overview

19→

Patents

2006–2021

Patent span

Physics

Primary field (CPC G)

Patents· 19 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing26%

G11CStatic stores21%

H03KPulse technique17%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use17%

G06TImage data processing or generation, in general10%

G06NComputing arrangements based on specific computational models2%

H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems2%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%

Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications2%

PatentTitleYear

10,909,652Enabling product SKUs based on chiplet configurations2021 10,817,012System, apparatus and method for providing a local clock signal for a memory array2020 10,803,548Disaggregation of SOC architecture2020 10,790,010System, apparatus and method for segmenting a memory array2020 10,754,809Reducing aging of register file keeper circuits2020 10,747,286Dynamic power budget allocation in multi-processor system2020 10,491,217Low-power clock gate circuit2019 10,409,319System, apparatus and method for providing a local clock signal for a memory array2019 10,347,324System, apparatus and method for segmenting a memory array2019 10,333,379Power switching circuitry including power-up control2019 10,324,721Reducing aging of register file keeper circuits2019 10,193,536Shared keeper and footer flip-flop2019 10,177,765Integrated clock gate circuit with embedded NOR2019 10,062,429System, apparatus and method for segmenting a memory array2018 9,947,388Reduced swing bit-line apparatus and method2018 9,859,876'Shared keeper and footer flip-flop'2018 9,685,208'Assist circuit for memory'2017 9,355,694'Assist circuit for memory'2016 7,130,236'Low power delay controlled zero sensitive sense amplifier'2006

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2006–2021Patents assigned to INTEL CORP (19)· patent assignee history

2006–2021Based in Roseville, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	19	2006–2021

Locations

Location	Patents	Span
Roseville, California, US	19	2006–2021