Inventor
YU-CHUNG LIEN
Inventor
US
Overview
Patents· 71 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores55%
H10BElectronic memory devices15%
G06FElectric digital data processing14%
H01LSemiconductor devices10%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%
H10DInorganic electric semiconductor devices2%
G01RMeasuring electric variables1%
H10NElectric solid-state devices not otherwise provided for1%
PatentTitleYear
12,597,476Program verify compensation in a memory device with a defective deck202612,580,031Level-based data refresh in a memory sub-system202612,567,468Pass voltage adjustment for program operation in a memory device with a defective deck202612,561,072Corrective read with parallel auto-read calibration in a memory sub-system202612,541,311Power management for memory devices with partially good blocks202612,537,060Programming delay scheme for in a memory sub-system based on memory reliability202612,537,068Half good block handling with defective deck pre-programing in a memory sub-system202612,525,304Reliability based data verification202612,450,154Selection of erase policy in a memory device202512,417,808Single-level cell programming with adaptive wordline ramp rate202512,417,026Adaptive sensing time for memory operations202512,417,028Dynamic erase operation selection using erase policy202512,373,116Dynamic read retry voltage sequences in a memory subsystem202512,333,160Memory read operation using a voltage pattern based on a read command type202512,254,926Memory device with fast write mode to mitigate power loss202512,249,378CELSRC voltage separation between SLC and XLC for SLC program average ICC reduction202512,248,697Dynamic read level trim selection for scan operations of memory devices202512,237,015Adaptive sensing time for memory operations202512,237,003Management of dynamic read voltage sequences in a memory subsystem202512,211,556Independent sensing times202512,197,739Adaptive bitline voltage for memory operations202512,189,961Charge loss mitigation through dynamic programming sequence202512,170,1173D NAND memory with built-in capacitor202412,154,635Memory programming techniques to reduce power consumption202412,148,4803D NAND memory with fast corrective read202412,142,326Adaptive programming delay scheme in a memory sub-system202412,106,812Detecting a memory write reliability risk without using a write verify operation202412,079,079Proximity based parity data management202412,073,905Adaptive error avoidance in the memory devices202412,067,255Error detection for programming single level cells202412,057,157Low power mode with read sequence adjustment202412,057,167Padding in flash memory blocks202412,027,210Programming delay scheme for a memory sub-system based on memory reliability202412,014,049Adaptive sensing time for memory operations202411,972,814Verify techniques for current reduction in a memory device202411,972,122Memory read operation using a voltage pattern based on a read command type202411,972,809Selective inhibit bitline voltage to cells with worse program disturb202411,972,801Program voltage dependent program source levels202411,972,803Word line zone dependent pre-charge voltage202411,894,081EP cycling dependent asymmetric/symmetric VPASS conversion in non-volatile memory structures202411,887,670Controlling bit line pre-charge voltage separately for multi-level memory cells and single-level memory cells to reduce peak current consumption202411,875,842Systems and methods for staggering read operation of sub-blocks202411,837,296Non-volatile memory with adjusted bit line voltage during verify202311,790,992State dependent VPVD voltages for more uniform threshold voltage distributions in a memory device202311,758,718Three dimensional memory device containing truncated channels and method of operating the same with different erase voltages for different bit lines202311,699,494Peak and average ICC reduction by tier-based sensing during program verify operations of non-volatile memory structures202311,664,075Sub-block programming mode with multi-tier block202311,600,343Efficient read of NAND with read disturb mitigation202311,587,619Block configuration for memory device with separate sub-blocks202311,521,686Memory apparatus and method of operation using state bit-scan dependent ramp rate for peak current reduction during program operation202211,508,450Dual time domain control for dynamic staggering202211,475,958Negative bit line biasing during quick pass write programming202211,475,959Reduced program time for memory cells using negative bit line voltage for enhanced step up of program bias202211,456,333Three-dimensional NAND memory device containing two terminal selector and methods of using and making thereof202211,417,400Controlling timing and ramp rate of program-inhibit voltage signal during programming to optimize peak current202211,398,280Lockout mode for reverse order read operation202211,386,968Memory apparatus and method of operation using plane dependent ramp rate and timing control for program operation202211,385,810Dynamic staggering for programming in nonvolatile memory202211,373,710Time division peak power management for non-volatile storage202211,361,835Countermeasure for reducing peak current during programming by optimizing timing of latch scan operations202211,355,208Triggering next state verify in progam loop for nonvolatile memory202211,335,413Ramp rate control for peak and average current reduction of open blocks202211,335,411Erase operation for memory device with staircase word line voltage during erase pulse202211,328,754Pre-charge timing control for peak current based on data latch count202211,315,648Dynamic tier selection for program verify in nonvolatile memory202211,270,776Countermeasure for reducing peak current during program operation under first read condition202211,250,892Pre-charge ramp rate control for peak current based on data latch count202211,226,772Peak power reduction management in non-volatile storage by delaying start times operations202211,211,127Loop dependent plane skew methodology for program operation202111,189,337Multi-stage voltage control for peak and average current reduction of open blocks202111,189,351Peak and average current reduction for sub block memory operation2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2025Patents assigned to SANDISK TECHNOLOGIES LLC (34)· patent assignee history
2021–2022Patents assigned to WESTERN DIGITAL TECH INC (5)· patent assignee history
2021–2026Based in US· patent location history
2024–2026Patents assigned to MICRON TECHNOLOGY INC (31)· patent assignee history
2024Patents assigned to SANDDISK TECH LLC (1)· patent assignee history
2026Patents assigned to MICRON TECH INC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SANDISK TECHNOLOGIES LLC | 34 | 2021–2025 |
| MICRON TECHNOLOGY INC | 31 | 2024–2026 |
| WESTERN DIGITAL TECH INC | 5 | 2021–2022 |
| MICRON TECH INC | 1 | 2026 |
| SANDDISK TECH LLC | 1 | 2024 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 71 | 2021–2026 |