Inventor
Ravikumar Ramachandran
Inventor
Pleasantville, NY, US
Overview
Patents· 103 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices35%
H01LSemiconductor devices22%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1016%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%
H10BElectronic memory devices7%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
C09GPolishing compositions1%
C09KMaterials for miscellaneous applications, not provided for elsewhere1%
B24BMachines, devices, or processes for grinding or polishing1%
C11DDetergent compositions1%
PatentTitleYear
10,832,971Fabricating tapered semiconductor devices202010,693,005Reliable gate contacts over active areas202010,573,646Preserving channel strain in fin cuts202010,424,576Standard cell architecture with at least one gate contact over an active area201910,424,574Standard cell architecture with at least one gate contact over an active area201910,403,628Finfet based ZRAM with convex channel region201910,381,480Reliable gate contacts over active areas201910,256,238Preserving channel strain in fin cuts201910,242,918Shallow trench isolation structures and contact patterning201910,242,980Semiconductor fin isolation by a well trapping fin portion201910,177,154Structure and method to prevent EPI short between trenches in FinFET eDRAM201910,177,039Shallow trench isolation structures and contact patterning201910,128,239Preserving channel strain in fin cuts201810,083,865Partial spacer for increasing self aligned contact process margins201810,074,562Self aligned contact structure20189,985,104Contact first replacement metal gate20189,929,047'Partial spacer for increasing self aligned contact process margins'20189,818,873'Forming stressed epitaxial layers between gates separated by different pitches'20179,818,741'Structure and method to prevent EPI short between trenches in FINFET eDRAM'20179,735,162'Dynamic random access memory cell with self-aligned strap'20179,577,068'Protection of semiconductor-oxide-containing gate dielectric during replacement gate formation'20179,564,443'Dynamic random access memory cell with self-aligned strap'20179,548,244'Self-aligned contact structure'20179,536,900'Forming fins of different semiconductor materials on the same substrate'20179,496,258'Semiconductor fin isolation by a well trapping fin portion'20169,496,362'Contact first replacement metal gate'20169,496,368'Partial spacer for increasing self aligned contact process margins'20169,431,395'Protection of semiconductor-oxide-containing gate dielectric during replacement gate formation'20169,431,399'Method for forming merged contact for semiconductor device'20169,397,175'Multi-composition gate dielectric field effect transistors'20169,368,593'Multiple thickness gate dielectrics for replacement gate field effect transistors'20169,349,649'Low resistance and defect free epitaxial semiconductor material for providing merged FinFETs'20169,349,650'Low resistance and defect free epitaxial semiconductor material for providing merged FinFETs'20169,337,200'Dynamic random access memory cell employing trenches located between lengthwise edges of semiconductor fins'20169,293,461'Replacement metal gate structures for effective work function control'20169,252,053'Self-aligned contact structure'20169,245,965'Uniform finFET gate height'20169,231,072'Multi-composition gate dielectric field effect transistors'20169,224,826'Multiple thickness gate dielectrics for replacement gate field effect transistors'20159,214,541'Self-aligned contact for replacement gate devices'20159,190,520'Strained finFET with an electrically isolated channel'20159,190,406'Fin field effect transistors having heteroepitaxial channels'20159,177,868'Annealing oxide gate dielectric layers for replacement metal gate field effect transistors'20159,099,393'Enabling enhanced reliability and mobility for replacement gate planar and FinFET structures'20159,082,851'FinFET having suppressed leakage current'20159,059,290'FinFET device formation'20159,059,134'Self-aligned contacts for high k/metal gate process flow'20159,029,913'Silicon-germanium fins and silicon fins on a bulk substrate'20158,933,528'Semiconductor fin isolation by a well trapping fin portion'20158,928,057'Uniform finFET gate height'20158,928,086'Strained finFET with an electrically isolated channel'20158,912,607'Replacement metal gate structures providing independent control on work function and gate leakage current'20148,829,617'Uniform finFET gate height'20148,815,693'FinFET device formation'20148,642,424'Replacement metal gate structure and methods of manufacture'20148,629,014'Replacement metal gate structures for effective work function control'20148,536,656'Self-aligned contacts for high k/metal gate process flow'20138,450,169'Replacement metal gate structures providing independent control on work function and gate leakage current'20138,436,427'Dual metal and dual dielectric integration for metal high-K FETs'20138,426,300'Self-aligned contact for replacement gate devices'20138,420,491'Structure and method for replacement metal gate field effect transistors'20138,236,637'Planar silicide semiconductor structure'20128,193,099'Protecting exposed metal gate structures from etching processes in integrated circuit manufacturing'20127,943,457'Dual metal and dual dielectric integration for metal high-k FETs'20117,838,908'Semiconductor device having dual metal gates and method of manufacture'20107,691,701'Method of forming gate stack and structure thereof'20107,670,901'Method of fabricating a bottle trench and a bottle trench capacitor'20107,528,027'Structure and method for manufacturing device with ultra thin SOI at the tip of a V-shape channel'20097,498,271'Nitrogen based plasma process for metal gate MOS device'20097,485,510'Field effect device including inverted V shaped channel region and method for fabrication thereof'20097,387,930'Method of fabricating a bottle trench and a bottle trench capacitor'20087,358,130'Method for monitoring lateral encroachment of spacer process on a CD SEM'20087,335,969'Method of monitoring introduction of interfacial species'20087,270,130'Semiconductor device cleaning employing heterogeneous nucleation for controlled cavitation'20077,202,187'Method of forming sidewall spacer using dual-frequency plasma enhanced CVD'20077,122,439'Method of fabricating a bottle trench and a bottle trench capacitor'20067,122,437'Deep trench capacitor with buried plate electrode and isolation collar'20067,105,398'Method for monitoring lateral encroachment of spacer process on a CD SEM'20066,933,192'Method for fabricating a trench having a buried dielectric collar'20056,929,964'Method of monitoring introduction on interfacial species'20056,908,806'Gate metal recess for oxidation protection and parasitic capacitance reduction'20056,887,761'Vertical semiconductor devices'20056,858,441'MRAM MTJ stack to conductive line alignment method'20056,849,153'Removal of post-rie polymer on A1/CU metal line'20056,740,568'Method to enhance epitaxial regrowth in amorphous silicon contacts'20046,723,611'Vertical hard mask'20046,716,734'Low temperature sidewall oxidation of W/WN/poly-gatestack'20046,630,074'Etching composition and use thereof'20036,579,766'Dual gate oxide process without critical resist and without N2 implant'20036,569,769'Slurry-less chemical-mechanical polishing'20036,443,811'Ceria slurry solution for improved defect control of silicon dioxide chemical-mechanical polishing'20026,358,855'Clean method for recessed conductive barriers'20026,358,850'Slurry-less chemical-mechanical polishing of oxide materials'20026,350,692'Increased polish removal rate of dielectric layers using fixed abrasive pads'20026,303,506'Compositions for and method of reducing/eliminating scratches and defects in silicon dioxide during CMP process'20016,274,440'Manufacturing of cavity fuses on gate conductor level'20016,149,830'Composition and method for reducing dishing in patterned metal during CMP process'20006,074,935'Method of reducing the formation of watermarks on semiconductor wafers'20006,060,398'Guard cell for etching'20005,980,770'Removal of post-RIE polymer on Al/Cu metal line'19995,934,299'Apparatus and method for improved washing and drying of semiconductor wafers'19995,932,493'Method to minimize watermarks on silicon substrates'19995,807,439'Apparatus and method for improved washing and drying of semiconductor wafers'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2020Patents assigned to IBM (87)· patent assignee history
1998–2005Patents assigned to SIEMENS AG (7)· patent assignee history
1998–2005Based in Beacon, NY, US· patent location history
2001–2010Patents assigned to INFINEON TECHNOLOGIES AG (12)· patent assignee history
2001–2003Based in Ossining, NY, US· patent location history
2003–2020Based in Pleasantville, NY, US· patent location history
2012–2014Patents assigned to RAMACHANDRAN RAVIKUMAR (9)· patent assignee history
2012–2013Based in Hopewell Junction, NY, US· patent location history
2015–2017Patents assigned to GLOBALFOUNDRIES INC (11)· patent assignee history
2017Based in Pleaseantville, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 87 | 1998–2020 |
| INFINEON TECHNOLOGIES AG | 12 | 2001–2010 |
| GLOBALFOUNDRIES INC | 11 | 2015–2017 |
| RAMACHANDRAN RAVIKUMARself | 9 | 2012–2014 |
| SIEMENS AG | 7 | 1998–2005 |
Locations
| Location | Patents | Span |
|---|---|---|
| Pleasantville, New York, US | 84 | 2003–2020 |
| Beacon, New York, US | 10 | 1998–2005 |
| Ossining, New York, US | 6 | 2001–2003 |
| Hopewell Junction, New York, US | 2 | 2012–2013 |
| Pleaseantville, New York, US | 1 | 2017 |