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Inventor

Michael Corwin

Inventor
Sunnyvale, CA, US

Overview

27→
Patents
2000–2020
Patent span
Physics
Primary field (CPC G)

Patents· 27 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing83%
H04LTransmission of digital information, e.g. telegraphic communication10%
G11CStatic stores7%
PatentTitleYear
10,803,066Methods and systems for hardware acceleration of database operations and queries for a versioned database based on multiple hardware accelerators20209,542,442'Accessing data in a column store database based on hardware compatible indexing and replicated reordered columns'20179,378,231'Accessing data in column store database based on hardware compatible data structures'20169,208,829'Designated memory sub-channels for computing systems and environments'20159,141,670'Methods and systems for hardware acceleration of streamed database operations and queries based on multiple hardware accelerators'20158,862,625'Accessing data in a column store database based on hardware compatible indexing and replicated reordered columns'20148,244,718'Methods and systems for hardware acceleration of database operations and queries'20128,234,267'Hardware accelerated reconfigurable processor for accelerating database operations and queries'20128,229,918'Hardware accelerated reconfigurable processor for accelerating database operations and queries'20128,224,800'Hardware accelerated reconfigurable processor for accelerating database operations and queries'20127,966,343'Accessing data in a column store database based on hardware compatible data structures'20117,952,997'Congestion management groups'20117,908,259'Hardware accelerated reconfigurable processor for accelerating database operations and queries'20117,606,968'Multi-level content addressable memory'20097,110,394'Packet switching apparatus including cascade ports and method for switching packets'20066,985,975'Packet lockstep system and method'20066,611,910'Method for processing branch operations'20036,591,359'Speculative renaming of data-processor registers'20036,550,001'Method and implementation of statistical detection of read after write and write after write hazards'20036,438,650'Method and apparatus for processing cache misses'20026,438,682'Method and apparatus for predicting loop exit branches'20026,378,063'Method and apparatus for efficiently routing dependent instructions to clustered execution units'20026,304,960'Validating prediction for branches in a cluster via comparison of predicted and condition selected tentative target addresses and validation of branch conditions'20016,240,510'System for processing a cluster of instructions where the instructions are issued to the execution units having a priority order according to a template associated with the cluster of instructions'20016,237,077'Instruction template for efficient processing clustered branch instructions'20016,092,188'Processor and instruction set with predict instructions'20006,016,542'Detecting long latency pipeline stalls for thread switching'2000

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2000–2003Patents assigned to INTEL CORP (9)· patent assignee history
2000–2003Based in Palo Alto, CA, US· patent location history
2002–2020Based in Sunnyvale, CA, US· patent location history
2011–2020Patents assigned to TERADATA US INC (12)· patent assignee history
2012–2016Patents assigned to BRANSCOME JEREMY (6)· patent assignee history
2012–2016Patents assigned to CHAMDANI JOSEPH I (6)· patent assignee history
2012–2016Patents assigned to CORWIN MICHAEL (6)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TERADATA US INC122011–2020
INTEL CORP92000–2003
BRANSCOME JEREMY62012–2016
CHAMDANI JOSEPH I62012–2016
CORWIN MICHAELself62012–2016
Locations
LocationPatentsSpan
Sunnyvale, California, US192002–2020
Palo Alto, California, US82000–2003