LexDanaLexDanabeta
Inventor

Hiroyuki Ode

Inventor
Higashihiroshima, JP

Overview

64→
Patents
2009–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 64 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices31%
H10BElectronic memory devices16%
H01LSemiconductor devices14%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%
H10NElectric solid-state devices not otherwise provided for6%
C23CCoating metallic material4%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
G11CStatic stores3%
H01GCapacitors3%
Y10TTechnical subjects covered by former us classification3%
PatentTitleYear
10,940,657Pouch container aligned structure, manufacturing device for same, and manufacturing method for same202110,211,259Semiconductor memory device and method of manufacturing the same201910,074,694Memory device and method for manufacturing the same20189,905,759'Memory device and method for manufacturing the same'20189,721,961'Semiconductor memory device'20179,704,922'Semiconductor memory device and method of manufacturing the same while avoiding process damage to a variable resistance film'20179,559,300'Resistive random access memory device and manufacturing method thereof'20179,418,737'Nonvolatile semiconductor memory device and method of controlling the same'20169,336,880'Nonvolatile memory device and method of controlling the same'20169,224,788'Nonvolatile memory device and method for manufacturing same'20159,224,878'High work function, manufacturable top electrode'20159,209,394'Resistance change element and method for manufacturing same'20159,178,010'Adsorption site blocking method for co-doping ALD films'20159,129,850'Semiconductor device manufacturing method'20159,105,646'Methods for reproducible flash layer deposition'20159,012,298'Methods for reproducible flash layer deposition'20158,975,633'Molybdenum oxide top electrode for DRAM capacitors'20158,912,628'Semiconductor device and method for manufacturing the same'20148,906,812'Wet etch and clean chemistries for MoOx'20148,878,269'Band gap improvement in DRAM capacitors'20148,853,049'Single-sided non-noble metal electrode hybrid MIM stack for DRAM devices'20148,847,397'High work function, manufacturable top electrode'20148,836,002'Method for fabricating a DRAM capacitor'20148,835,273'High temperature ALD process of metal oxide for DRAM applications'20148,829,647'High temperature ALD process for metal oxide for DRAM applications'20148,828,836'Method for fabricating a DRAM capacitor'20148,813,325'Method for fabricating a DRAM capacitor'20148,815,695'Methods to improve leakage for ZrO2 based high K MIM capacitor'20148,815,677'Method of processing MIM capacitors to reduce leakage current'20148,779,607'Devices with covering layer and filler'20148,772,123'Band gap improvement in DRAM capacitors'20148,765,570'Manufacturable high-k DRAM MIM capacitor structure'20148,765,569'Molybdenum oxide top electrode for DRAM capacitors'20148,748,325'Method of manufacturing semiconductor device'20148,722,504'Interfacial layer for DRAM capacitor'20148,679,939'Manufacturable high-k DRAM MIM capacitor structure'20148,652,927'Integration of non-noble DRAM electrode'20148,647,943'Enhanced non-noble electrode layers for DRAM capacitor cell'20148,647,960'Anneal to minimize leakage current in DRAM capacitor'20148,609,469'Method of manufacturing semiconductor device'20138,581,318'Enhanced non-noble electrode layers for DRAM capacitor cell'20138,581,319'Semiconductor stacks including catalytic layers'20138,574,999'Blocking layers for leakage current reduction in DRAM devices'20138,574,983'Method for fabricating a DRAM capacitor having increased thermal and chemical stability'20138,574,998'Leakage reduction in DRAM MIM capacitors'20138,575,671'Asymmetric MIM capacitor for DRAM devices'20138,574,997'Method of using a catalytic layer to enhance formation of a capacitor stack'20138,569,818'Blocking layers for leakage current reduction in DRAM devices'20138,569,819'Doped electrodes for DRAM applications'20138,563,392'Method of forming an ALD material'20138,546,236'High performance dielectric stack for DRAM capacitor'20138,541,868'Top electrode templating for DRAM capacitor'20138,542,523'Method for fabricating a DRAM capacitor having increased thermal and chemical stability'20138,541,283'High performance dielectric stack for DRAM capacitor'20138,541,282'Blocking layers for leakage current reduction in DRAM devices'20138,530,348'Integration of non-noble DRAM electrode'20138,486,780'Doped electrode for dram applications'20138,476,141'High performance dielectric stack for DRAM capacitor'20138,440,537'Adsorption site blocking method for co-doping ALD films'20138,435,854'Top electrode templating for DRAM capacitor'20138,415,227'High performance dielectric stack for DRAM capacitor'20138,349,696'Asymmetric MIM capacitor for DRAM devices'20138,211,229'Apparatus including column having hollow part filled with filler and solid film-formation material'20127,592,267'Method for manufacturing semiconductor silicon substrate and apparatus for manufacturing the same'2009

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2009–2015Patents assigned to ELPIDA MEMORY INC (40)· patent assignee history
2009–2015Based in Tokyo, JP· patent location history
2012–2014Patents assigned to ODE HIROYUKI (26)· patent assignee history
2013–2015Patents assigned to INTERMOLECULAR INC (46)· patent assignee history
2013–2014Patents assigned to DEWEERD WIM (15)· patent assignee history
2013–2014Patents assigned to CHEN HANHONG (14)· patent assignee history
2013–2015Based in Higashihiroshima, JP· patent location history
2013–2014Based in Hiroshima, JP· patent location history
2015–2019Based in Mie, JP· patent location history
2016–2018Based in Yokkaichi, JP· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
INTERMOLECULAR INC462013–2015
ELPIDA MEMORY INC402009–2015
ODE HIROYUKIself262012–2014
DEWEERD WIM152013–2014
CHEN HANHONG142013–2014
Locations
LocationPatentsSpan
Higashihiroshima, JP382013–2015
Hiroshima, JP82013–2014
Yokkaichi, JP72016–2018
Tokyo, JP72009–2015
Mie, JP32015–2019