Inventor
Cory E. Weber
Inventor
Hillsboro, OR, US
Overview
Patents· 26 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices41%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1027%
H01LSemiconductor devices22%
B82YSpecific uses or applications of nanostructures3%
H10BElectronic memory devices3%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation3%
PatentTitleYear
10,847,653Semiconductor device having metallic source and drain regions202010,847,635Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices202010,840,366Nanowire structures having wrap-around contacts202010,600,810Backside fin recess control with multi-hsi option202010,497,781Methods for doping a sub-fin region of a semiconductor structure by backside reveal and associated devices201910,483,385Nanowire structures having wrap-around contacts201910,411,090Hybrid trigate and nanowire CMOS device architecture201910,304,946Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices201910,084,087Enhanced dislocation stress transistor20189,660,078'Enhanced dislocation stress transistor'20179,583,487'Semiconductor device having metallic source and drain regions'20179,231,076'Enhanced dislocation stress transistor'20169,076,814'Enhanced dislocation stress transistor'20158,779,477'Enhanced dislocation stress transistor'20148,716,806'Methods of channel stress engineering and structures formed thereby'20148,193,049'Methods of channel stress engineering and structures formed thereby'20127,851,291'Epitaxial silicon germanium for reduced contact resistance in field-effect transistors'20107,566,605'Epitaxial silicon germanium for reduced contact resistance in field-effect transistors'20097,226,824'Nitrogen controlled growth of dislocation loop in stress enhanced transistor'20077,226,843'Indium-boron dual halo MOSFET'20077,187,057'Nitrogen controlled growth of dislocation loop in stress enhanced transistor'20077,129,533'High concentration indium fluorine retrograde wells'20066,838,329'High concentration indium fluorine retrograde wells'20056,800,887'Nitrogen controlled growth of dislocation loop in stress enhanced transistor'20046,410,359'Reduced leakage trench isolation'20026,215,165'Reduced leakage trench isolation'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2020Patents assigned to INTEL CORP (26)· patent assignee history
2001–2002Based in Beaverton, OR, US· patent location history
2004–2020Based in Hillsboro, OR, US· patent location history
2012–2014Patents assigned to DESHPANDE HEMANT (3)· patent assignee history
2012–2014Patents assigned to WEBER CORY (3)· patent assignee history
2012–2014Patents assigned to ASHUTOSH ASHUTOSH (2)· patent assignee history
2012–2014Patents assigned to GOLONZKA OLEG (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 26 | 2001–2020 |
| DESHPANDE HEMANT | 3 | 2012–2014 |
| WEBER CORYself | 3 | 2012–2014 |
| ASHUTOSH ASHUTOSH | 2 | 2012–2014 |
| GOLONZKA OLEG | 2 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hillsboro, OR, US | 24 | 2004–2020 |
| Beaverton, OR, US | 2 | 2001–2002 |